System studio icc cross-compiling issues.

System studio icc cross-compiling issues.

I've compiled a helloworld program using icc, but it wouldn't run on a yocto-linux OS on the Bay Tail board.

The error information shows that:

bash: ./helloicc : No such file or directory

I'm pretty sure there is no problem with the location of file, and it's excutable.

After that I've tried to add parameters along with icc to compile my source file, but get the same issue.

That's how I compile my source file.

icc -xATOM_SSE4.2 -mtune=atom <file.c> -o <output>

I suppose I didn't get the target option right, which one should I choose?

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A piece of help document from icc -help

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-x<code>  generate specialized code to run exclusively on processors
          indicated by <code> as described below

            SSE2    May generate Intel(R) SSE2 and SSE instructions for Intel
                    processors.  Optimizes for the Intel NetBurst(R)
                    microarchitecture.
            SSE3    May generate Intel(R) SSE3, SSE2, and SSE instructions for
                    Intel processors.  Optimizes for the enhanced Pentium(R) M
                    processor microarchitecture and Intel NetBurst(R)
                    microarchitecture.

            SSSE3   May generate Intel(R) SSSE3, SSE3, SSE2, and SSE
                    instructions for Intel processors.  Optimizes for the
                    Intel(R) Core(TM) microarchitecture.

            SSE4.1  May generate Intel(R) SSE4 Vectorizing Compiler and Media
                    Accelerator instructions for Intel processors.  May
                    generate Intel(R) SSSE3, SSE3, SSE2, and SSE instructions
                    and it may optimize for Intel(R) 45nm Hi-k next generation
                    Intel Core(TM) microarchitecture.

            SSE4.2  May generate Intel(R) SSE4 Efficient Accelerated String
                    and Text Processing instructions supported by Intel(R)
                    Core(TM) i7 processors.  May generate Intel(R) SSE4
                    Vectorizing Compiler and Media Accelerator, Intel(R) SSSE3,
                    SSE3, SSE2, and SSE instructions and it may optimize for
                    the Intel(R) Core(TM) processor family.
            AVX     May generate Intel(R) Advanced Vector Extensions (Intel(R)
                    AVX), Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3,
                    SSE2, and SSE instructions for Intel(R) processors.
            CORE-AVX2
                    May generate Intel(R) Advanced Vector Extensions 2
                    (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3,
                    SSE2, and SSE instructions for Intel(R) processors.
            CORE-AVX-I
                    May generate Intel(R) Advanced Vector Extensions (Intel(R)
                    AVX), including instructions in Intel(R) Core 2(TM)
                    processors in process technology smaller than 32nm,
                    Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE
                    instructions for Intel(R) processors.

            ATOM_SSE4.2
                    May generate MOVBE instructions for Intel(R) processors,
                    depending on the setting of option -minstruction.
                    May also generate Intel(R) SSE4.2, SSE3, SSE2, and SSE
                    instructions for Intel processors. Optimizes for Intel(R)
                    Atom(TM) processors that support Intel(R) SSE4.2 and MOVBE
                    instructions.
            ATOM_SSSE3
                    May generate MOVBE instructions for Intel(R) processors,
                    depending on the setting of option -minstruction.
                    May also generate Intel(R) SSSE3, SSE3, SSE2, and SSE
                    instructions for Intel processors. Optimizes for the
                    Intel(R) Atom(TM) processor that support Intel(R) SSE
                    and MOVBE instructions.
            MIC-AVX512
                    May generate Intel(R) Advanced Vector Extensions 512
                    (Intel(R) AVX-512) Foundation instructions, Intel(R)
                    AVX-512 Conflict Detection instructions, Intel(R) AVX-512
                    Exponential and Reciprocal instructions, Intel(R) AVX-512
                    Prefetch instructions for Intel(R) processors, and the
                    instructions enabled with CORE-AVX2. Optimizes for Intel(R)
                    processors that support Intel(R) AVX-512 instructions.

-xHost    generate instructions for the highest instruction set and processor
          available on the compilation host machine

-ax<code1>[,<code2>,...]
          generate code specialized for processors specified by <codes>
          while also generating generic IA-32 instructions.  
          <codes> includes one or more of the following:

            SSE2    May generate Intel(R) SSE2 and SSE instructions for Intel
                    processors.
            SSE3    May generate Intel(R) SSE3, SSE2, and SSE instructions for
                    Intel processors.

            SSSE3   May generate Intel(R) SSSE3, SSE3, SSE2, and SSE
                    instructions for Intel processors.

            SSE4.1  May generate Intel(R) SSE4.1, SSSE3, SSE3, SSE2, and SSE
                   instructions for Intel processors.

            SSE4.2  May generate Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3, SSE2,
                    and SSE instructions for Intel processors.
            AVX     May generate Intel(R) Advanced Vector Extensions (Intel(R)
                    AVX), Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3,
                    SSE2, and SSE instructions for Intel(R) processors.
            CORE-AVX2
                    May generate Intel(R) Advanced Vector Extensions 2
                    (Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3,
                    SSE2, and SSE instructions for Intel(R) processors.
            CORE-AVX-I
                    May generate Intel(R) Advanced Vector Extensions (Intel(R)
                    AVX), including instructions in Intel(R) Core 2(TM)
                    processors in process technology smaller than 32nm,
                    Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE
                    instructions for Intel(R) processors.
            MIC-AVX512
                    May generate Intel(R) Advanced Vector Extensions 512
                    (Intel(R) AVX-512) Foundation instructions, Intel(R)
                    AVX-512 Conflict Detection instructions, Intel(R) AVX-512
                    Exponential and Reciprocal instructions, Intel(R) AVX-512
                    Prefetch instructions for Intel(R) processors, and the
                    instructions enabled with CORE-AVX2.

-mcpu=<cpu>
          same as -mtune=<cpu>

-mtune=<cpu>
          optimize for a specific <cpu>
            slm        - processors that support Intel(R) SSE4.2 and MOVBE
                         instructions
            core-avx2  - processors that support Intel(R) Advanced Vector
                         Extensions 2 (Intel(R) AVX2)
            core-avx-i - processors that support Intel(R) Advanced Vector
                         Extensions (Intel(R) AVX), including instructions in
                         Intel(R) Core 2(TM) processors in process technology
                         smaller than 32nm
            corei7-avx - processors that support Intel(R) Advanced Vector
                         Extensions (Intel(R) AVX)
            corei7     - processors that support Intel(R) SSE4 Efficient
                         Accelerated String and Text Processing instructions
            atom       - processors that support MOVBE instructions
            core2      - Intel(R) Core 2(TM) processor family
            pentium-m  - Intel(R) Pentium(R) M processors
            pentium4   - Intel(R) Pentium(R) 4 processors
            pentium3   - Intel(R) Pentium(R) III processors (Linux only)

-march=<cpu>
          generate code exclusively for a given <cpu>
            slm        - processors that support Intel(R) SSE4.2 and MOVBE
                         instructions
            core-avx2  - processors that support Intel(R) Advanced Vector
                         Extensions 2 (Intel(R) AVX2)
            core-avx-i - processors that support Intel(R) Advanced Vector
                         Extensions (Intel(R) AVX), including instructions in
                         Intel(R) Core 2(TM) processors in process technology
                         smaller than 32nm
            corei7-avx - processors that support Intel(R) Advanced Vector
                         Extensions (Intel(R) AVX)
            corei7     - processors that support Intel(R) SSE4 Efficient
                         Accelerated String and Text Processing instructions
            atom       - processors that support MOVBE instructions
            core2      - Intel(R) Core 2(TM) processor family
            pentium-m  - Intel(R) Pentium(R) M processors
            pentium4   - Intel(R) Pentium(R) 4 processors
            pentium3   - Intel(R) Pentium(R) III processors (Linux only)

-msse3    May generate Intel(R) SSE3, SSE2, and SSE instructions

-mssse3   May generate Intel(R) SSSE3, SSE3, SSE2, and SSE instructions

-msse4    Enable -msse4.2

-msse4.1  May generate Intel(R) SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions

-msse4.2  May generate Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE
          instructions

-mavx     May generate Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE
          instructions

-masm=<dialect>
          generate asm instructions specified by <dialect>, which may be
          att (DEFAULT) or intel

-mmic     build an application that runs natively on Intel(R) MIC Architecture

-minstruction=<keyword>
          Refine instruction set output for the selected target processor

            [no]movbe  - Do/do not generate MOVBE instructions with ATOM_SSSE3
                          (requires -xATOM_SSSE3)
           

-f[no-]omit-frame-pointer
          enable(DEFAULT)/disable use of EBP as general purpose register.
          -fno-omit-frame-pointer replaces -fp

-f[no-]exceptions
          enable/disable(DEFAULT) C++ exception handling table generation

-fnon-call-exceptions
          enable/disable(DEFAULT) code that allows exceptions from trapping
          instructions to be caught

-regcall  make __regcall the default calling convention

-hotpatch[=n]
          generate padding bytes for function entries to enable image
          hotpatching. If specified, use 'n' as the padding.

-fasynchronous-unwind-tables
          determines whether unwind information is precise at an instruction
          boundary or at a call boundary.  -fno-asynchronous-unwind-tables is
          the default for IA-32 architecture.

-fextend-arguments=[32|64]
          By default, unprototyped scalar integer arguments are passed
          in 32-bits (sign-extended if necessary).
          On Intel(R) 64, unprototyped scalar integer arguments may be
          extended to 64-bits.

 

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Last post
For more complete information about compiler optimizations, see our Optimization Notice.

Hello,

Please refer to the training slides to understand how to build for a target system (Yocto):

https://software.intel.com/sites/default/files/Intel-System-Studio-2014.pdf

To build for yocto, you need to use the option "-platform=yl13" and Yocto environment variables.

Suggestion: figure out how to use Yocto GCC to make sure you understand the 'cross-compiling' process. To use ICC for Yocto, you need to first of all set up the GCC toolchain for Yocto.

Let me know if you still cannot figure it out, and I may clarify more details to you.

Thanks,

Shenghong

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