Micro-ops? X86 to Micro-ops?

Micro-ops? X86 to Micro-ops?

Hi All:

I've been doing research on Sun processors such as the Niagaras and on IBM power. I'm now switching to Intel; my current machine has a Core 2 Quad processor.

Anyways, one of the most troubling questions I've been trying to answer is:

Since IA32/Intel64 CISC instructions are broken down into RISC-like simpler micro-ops (uops), what are those uops? Does anyone know?

I don't want to know the exact uops used by Intel. I just want to get an idea of how many uops are common, medium, and more complex instructions broken into.

Is there a document that can give me an idea of which instructions break into more than 4 uops (which in turn require the use of micro-code sequencer in some architectures) ?

Any comments/answers are appreciated.



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Hi Arrazem,

Hmm. I've provided links to architectural resources on our Academic Community page.


You can salso try - http://www.intel.com/technology/architecture-silicon/microarchitecture.htm

If that does not help, let me know,


Thanks Paul for trying to help. Unfortunately, those links did not help. I also have all the Intel 64 & IA-32 Architectures Software Developer's Manuals and other manuals ordered from Intel. They do not contain what I'm looking for, though.
That's the reason why I came here to look maybe somone could help.

Thanks again.


Microops are lower level or more primitive instructions which can directly operate on various CPU internal units like ALU or SIMD and load/store facilities.If I am correct possible implementation of machine code fsin instruction could be broken down into a few or more microops.Some of them will be load/store and the other wll operate on internal register file and on FP add and mul  units.

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