I've been doing research on Sun processors such as the Niagaras and on IBM power. I'm now switching to Intel; my current machine has a Core 2 Quad processor.
Anyways, one of the most troubling questions I've been trying to answer is:
Since IA32/Intel64 CISC instructions are broken down into RISC-like simpler micro-ops (uops), what are those uops? Does anyone know?
I don't want to know the exact uops used by Intel. I just want to get an idea of how many uops are common, medium, and more complex instructions broken into.
Is there a document that can give me an idea of which instructions break into more than 4 uops (which in turn require the use of micro-code sequencer in some architectures) ?
Any comments/answers are appreciated.