I hope this is the right forum to ask about this issue.
I read at several articles ( ~1 year old ) how to align memory addresses so they fit cache lines. I was wondering why does it required? Doesn't the compiler knows the best alignment of the addresses? Couldn't the dynamic allocation decide the best alignment during run time depending on the specific HW it runs on? Is it possible that the program (processor) during run time will detect frquent misses when addressing specific addresses in small sequence of operations (i.e. detect a small and frequent "pattern" that really hits performance) and decide to change the data addresses to aligned address internally (completely transparenin to the user)?
The second issue is how to detect potential performance gain from memory alignment on a given code. I assume running VTune and having tons of cache misses might indicate memory alignment issue. Is there a better or more accurate indication and solution for this issue?