Beta Course Instructional Design Document: Multi-core Faculty Training 2.1 (3 day ILT class)

Beta Course Instructional Design Document: Multi-core Faculty Training 2.1 (3 day ILT class)

Instructional Design Document

Version 08262008

1. Course Name

Intel Software College Multicore Faculty Training 2.1

2. Writers

[Intel Confidential list]

3. Targeted availability

End of Q4, 2008

4. Brief Course Description

Proposed Course Duration: 3 days (21 hours) of lecture & labs. Targeted blend of lecture to lab is 60% lecture, 30% lab

This courseware provides an introduction to Intel Multi-Core Architecture and provides a complete survey of the importance of parallelism, threading concepts, multithreading methodology and programming with threads (Windows*, OpenMP* 3.0). It does so by means of lectures combined with important walk-through examples and topical hands-on lab exercises.

The course also includes an overview of performance analysis for Multi-Core platforms using the latest Intel threading tools. (Intel Software College offers onsite faculty trainings of this course to selected institutions of higher education). This course targets university level faculty of computer science-related courses, or programming courses in other departments such as mathematics and engineering, and engineering science

5. Needs Analysis

This class will provide faculty with a survey of available, downloadable ISC materials related to parallelism and visual computing, as well as an introduction to Intel software tools which makes parallelizing applications easier, faster and more robust.

Faculty benefit by gaining insight into the very latest trends in industry regarding tools and methodologies used for parallelism. The facultys students will benefit by taking more up to date technology -relevant curriculum components especially in regard to the most important parallelism concepts.

For returning faculty, Intel has changed the offerings to have more focus on visual computing workloads that are critical in todays business world, and have also updated the materials to reflect recent changes in computing trends, that is, more computing cores per system now than previously used. Further, recent changes to software tools including those to reflect the recent adoption of the OpenMP 3.0 spec are discussed.. Also new this year are changes to the Intel materials to suggest the categor
y of CS courses a given module might best be applied to in a typical university environment.

6. Subject Matter Experts (SMEs)

Subject Matter Experts who contributed material and time to the content of this courseware including structural, language, and technical edits are:

a. [Intel Confidential list]

7. Learner Analysis

Target Faculty population

This instructor-led course directly targets university-level faculty of computer science-related courses, or programming courses in other departments such mathematics and engineering, and engineering science.

Enrollees who would benefit most include professors and graduate students of post-secondary institutions of higher education, and other appropriate instructors who teach computer science, mathematics, logic, IT, information management, or any classes requiring the creation of, or alteration to, end-user or IT applications.

Currently these instructor-led classes focus on an audience that can read and understand English.

The preferred enrollee is an experienced computer scientist and has a good understanding of C/C++ programming language, to make best use of the lab materials. Typically this means 1-3 years programming experience with C/C++.

For attendees with little C/C++ experience, 1-3 years programming experience with Java or C# will suffice, and will facilitate understanding with the labs as well.

For hands-on parts of the material, a familiarity with MS Visual Studio IDE is a must, between 1-2 years; and specifically, attendees must know how to:

create a basic solution/project (we will be creating primarily command line-based projects

change compiler switches

set break points

successfully build projects

There is no entry requirement as to current threading knowledge or parallel programming models.

Instructors should be familiar with MS Windows* XP or Vista for the purposes of attending this training, but the downloadable materials will adapt easily for Linux. Additionally, some Linux labs will be available for download and use.

Some familiarity with application profiling software, and the profiling of applications would also be helpful t
o the attendee.

IF YOU HAVE NO EXPERIENCE, then consider doing the following course pre-work:

1) Downloading tutorials on using MS Visual Studio to create simple command line based hello world projects

2) Downloading labs and tutorials on the use of Intel VTune Analyzer, which come with the product, which can be downloaded here:

3) Downloading labs and tutorials on the use of the Intel C++ Compiler which show how to integrate the Intel compiler into the Microsoft Visual studio environment. The compiler is also available for downloading and evaluation here:

Target Student population

The student populations, indirectly targeted for the materials that are surveyed during this training, are undergraduate students in Computer Science, Math, Engineering or the sciences who design, alter, or implement applications. These undergraduate students are assumed to have little or no exposure to threading or other industry standard parallel programming models.

Some programming experience would be most helpful, but materials for a wide spectrum of experience levels are included. Most modules will focus more on upper level undergraduates, where C/C++ is required, while a few modules will focus on the lower level student where no Java or C/C++ is required.

After taking this course, the enrollee will be able to create exercises, relevant student projects, and highly customized lecture materials for undergraduates or other qualified programming students on:

1) The use of software tools for efficient parallelism analysis and code correctness,

2) Parallelism methodologies & patterns that the industry is currently using,

3) Parallelism implementations such as threading using Windows* ,OpenMP, or Threading Building Blocks,

Special notes for Faculty Training learners/attendees

Faculty Training (FT) attendees are special cases wherein they likely have more experience than the usual target audience for this class, and, they have the immediate goal of teaching this class in a live classroom environment with targeted students.

Ideal FT candidates for this material
have the following traits:

Currently instruct or plan to instruct adult students who fit in the learner description earlier in this section

Currently using a successful programming curriculum, or intend to soon create or teach one

Currently has multimedia processing experience

NOTE: There are no inherent limitations for instructors based on the experience or lack of it with regard to these objectives and content

Further, the course materials will use Intel software tools to easily illuminate important concepts, but those concepts can be explained and exploited using many other tools.

8. Context Analysis

The purpose of a Context Analysis is to identify and describe the environmental factors that inform the design of this module. Environmental factors include:

a. Learning Activities


Hands on labs


Round table discussions

b. Media Selection

No Tapes, CDs, or DVDs are available or provided

Electronic files are provided

Can be printed out for classroom use if desired

c. Participant Materials and Instructor Guides

Lecture presentation is .PPT format

lab document (may be .rtf, .doc, or .pdf), with software

lab validation document

Instructor Notes

A breeze training tutorial will be created during beta delivery for instructors planning to deliver this training

d. Packaging and production of training materials, and their mode of availability

Individual modules will be posted to for download

Posting of class in entirety will be to online repository: Multi-Core Courseware Content from Intel

e. Training Schedule.

Alpha & beta training classes will be recorded for use by instructors leading the 2.1 faculty training. The training schedule is not finalized but the expectation is that training will begin in the last half of Q4 2008. Written transcripts of these recordings will become part of the Instructor Notes.

9. Task Analysis

The relevant Job/Task Analysis for this material is defined by the Software Engineering Body of Knowledge (SWEBOK) and can be viewed in detail here:

The primary Bodies of Knowledge (BKs) used include, but are not limited to:

Software Requirements BK

Software Design BK

Key issues in Software Design (Concurrency)

Data persistence, etc.

Software Construction BK

Software Construction Fundamentals

Managing Construction

Practical Considerations (Coding, Construction Testing, etc.)

Relevant IEEE standards for relevant job activities include but are not limited to:

Standards in Construction, Coding, Construction Quality IEEE12207-95

(IEEE829-98) IEEE Std 829-1998, IEEE Standard for Software Test Documentation, IEEE, 1998.

(IEEE1008-87) IEEE Std 1008-1987 (R2003), IEEE Standard for Software Unit Testing, IEEE, 1987.

(IEEE1028-97) IEEE Std 1028-1997 (R2002), IEEE Standard for Software Reviews, IEEE, 1997.

(IEEE1517-99) IEEE Std 1517-1999, IEEE Standard for Information Technology-Software Life Cycle Processes- Reuse Processes, IEEE, 1999.

(IEEE12207.0-96) IEEE/EIA 12207.0-1996//ISO/IEC12207:1995, Industry Implementation of Int. Std. ISO/IEC 12207:95, Standard for Information Technology-Software Life Cycle Processes, IEEE, 1996.

10. Concept Analysis

Course Agenda

Introduction to Intel Multi-Core Architecture

Maximizing Application Performance with Intel Software Development Tools

Multi-Core Programming: Basic Concepts

Programming with Threads (Windows*, OpenMP* 3.0)

Threaded Programming Methodology

De-bugging & Tuning Threaded Applications

Day 1 Agenda:

0900 - Introductions

0930 Overview of modules/teaching strategies

Intel Core Duo Architecture

Using Intel Compilers

Using the
VTune Performance Analyzer

Using the OpenMP

1200 - Lunch

1300 - Overview of modules/teaching strategies

Design Patterns


Thread Checker

Thread Profiler

Tools Methodology

1630 Wrap up discussion

Day2 Agenda:

0900 - Programming with OpenMP* (introducing OpenMP 3.0)

1100 Parallel Design Patterns

1200 - Lunch

1300 - Parallel Design Patterns

1400 - Programming with TBB

1500 - P Threads/ Win Thread comparison

1630 - Wrap up discussion

Day3 Agenda:

0900 Debugging Threaded Applications: Using Intel Thread Checker

1100 - Tuning Threaded Applications: Using the Intel Thread Profiler

1200 - Lunch

1300 - Tuning Threaded Applications: Using the Intel Thread Profiler Threaded Programming Methodology

1400 - Tools Methodology (with VC workload)

1630 - Wrap-up and Evaluation

11. Learning Objectives

After completing this course, you should be able to:

Describe Intel Multi-Core Architecture at a high level (what is multi-core, why is multi-core important)

Gain an understanding of how to Develop well-optimized threaded applications and to improve application performance on Intel Multi-Core Architecture

More specifically you will be able to define and identify:

threads, data races, deadlocks, domain decomposition, functional decomposition, some parallel design patterns

Gain experience using tools deigned to track threading related issues

Implement parallelism on existing serial applications using hands on labs as examples

12. Criterion Items

Analyze sample code - Is this a data race? Why?

Analyze sample code - Is this a potential deadlock? Why?

Define a data race.

Name three ways to avoid data races

Define deadlock.

Why are data races problems for your code?

Why are deadlocks problems for your code?

What locking strategy can help to avoid deadlocks?

Given the following code, point to potential problems as discussed in the course materials provide pseudo code solution.

Provide real code solution.

Given the following code, which decomposition strategy is more appropriate? Defend your answer.

Does the following code access memory in a unit stride access pattern?

How can the following code be modified to access data in a unit stride access?

What is false sharing?

How can false sharing be avoided?

The Intel Th
read Checker shows the following screen what issue is being reported? What two lines of source code should be scrutinized?

The Intel Thread Profiler shows the following screen what issue is being reported? Given the source code below given an example of how to correct the issue

13. Expert Appraisal

Completed previously, module by module

14. Developmental Testing

Targeting Q4 08 delivery

Alpha materials will be unit (module tested) via peer review. Beta materials will ideally be taught to live audience for participant feedback

All labs will be validated on ISC delivery hardware and a validation document generated describing expected lab results on the given hardware & software platforms chosen for delivery

15. Production

Modules will posted to the Academic community download repository as they become available

For the 3 day course as an entity, the materials will be posted to a share on isc-server1 (ISC-SERVER1/Classes Released) for delivery by the Content Delivery team.


2 posts / 0 new
Last post
For more complete information about compiler optimizations, see our Optimization Notice.

Wow Bob, this looks like a great survey class. Good work!



Leave a Comment

Please sign in to add a comment. Not a member? Join today