About Sandy Bridge to Ivy bridge

About Sandy Bridge to Ivy bridge

I read here that new Ivy bridge must use socket LGA 1155
I am already perfectly satisfied Sandy Bridge but just an question
Mother board that have already for example G620 icore xx etc.... also using LGA 1155 will possible receive an upgrade with new to Ivy Bridge ?
Have you an link where is described details characteristics more complete ?
I have already difficulty to understand side graphic hosted posisition sandy bridge
when i use lspci linux system with sandy bridge processor G620
I show
00:02.0 VGA compatible controler: Intel Corporation Sandy Bridge Integrated Graphics Controler (rev 09)
I have rebuild all source in relation graphic (Mesa and all incuded)
I have rewrite an file xorg.conf correctly appropriated
Xrandr -q
confirm now that i have 1280*1024
video working very well but i use driver vesa .. with intel driver, is always rejected by xorg server...
Your data base about G620 give an warning about graphic could be not ???
Have you also an link where is described details characteristics graphic more complete ?

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For more complete information about compiler optimizations, see our Optimization Notice.

Hi ...
Here Intel and i observe that no one can answer two simples questions ?
I want use the Intel processors that I bought,correctly with his characteristics documented
and no with way approximately using nose .

This is not the right forum for your question. Let me move your thread/question to a Processor related forum to see if you can get some answers there.



Did you inform the OP of which forum you moved the thread to?



Ihave not moved the thread, but is looking for which forum still. I'll update here soon.


Hi and thank you for at least an response ..
You site have no section for answers to programing drivers.
Also for me is not problem bug with compiler GCC or ICC,
I have already compile success all package Linux have graphics relation.
I wait only technical characteristics for is rectified some sources for it work better.
Now, in the last version kernel several ,firmwares are separate and is better same for preserving
free Linux kernel independent.
For IVY and SANDY one of my customer have already several machines model SANDY have request to
me if futures his machines
could be upgrade IVY,only after this first confirmation
i must verify if with some flags compiler specifics the binary ready compatible two sides
Here ,is for compiler C/C++ I think , no ?

There is a good forum for such questions: http://communities.intel.com/community/tech/processors?view=discussions

But I can not move your thread there. It's from two different forum programs. You can repost the question there.


Thank you very much for the link Jennifer.
This Site require registering an new account...
I will see later.

Hello Jennifer
registering account on your link not working for me
after the procedure registering I don't receive the mail confirmation... ??
(I have tested on three different PPP connections)
I have answer my customer less complex to me , in futures he made the upgrade complete AMD or ARM...
(is just an kidding)

emmmm, I encountered the same problem. I'm looking for helper right now.....


There is a bug on the other forum registration. The issue has been escalated. Please hold on ....


Thank, Jennifer for all your answers
Here ,all servers using very complex routing, i have always doubt
It's the cause of the problem with server distant.
As You having also the problem I am reassured.

Hi Jennifer
I don't know if my customer already his retirement but mail confirmation of your link work now ....

For help you on the relation of my questions and c/c++ that have also value on this site.

GCC 4.7 is ready now but (frozen for release)
New flag for IVY & Haswell...

Support for new Intel processor codename IvyBridge with RDRND, FSGSBASE and F16C is available through -march=core-avx-i.
Support for the new Intel processor codename Haswell with AVX2, FMA, BMI, BMI2, LZCNT is available through -march=core-avx2.

Fortunately Them at least they are very effective and also are informed actualized for the new hardware.

Hi Jennifer
I don't know if my customer already his retirement but mail confirmation of your link work now ....

For help you on the relation of my questions and c/c++ that have also value on this site.

GCC 4.7 is ready now but (frozen for release)
New flag for IVY & Haswell...

Support for new Intel processor codename IvyBridge with RDRND, FSGSBASE and F16C is available through -march=core-avx-i.
Support for the new Intel processor codename Haswell with AVX2, FMA, BMI, BMI2, LZCNT is available through -march=core-avx2.

Fortunately Them at least they are very effective and also are informed actualized for the new hardware.

Thanks for this info.

I was checking the log-in this morning with my other email account, just saw your response now.

This is great.



I have build sources Gcc 4.7 and test with 450 sources
He work very very very well for me... (improved evident)
Extraordinary with Sandy Bridge ...(only this model i have testing)
Congratulation friends Team Gnu compiler, yet an work fabulous ..

If i use flag -march=core-avx-i to Sandy Bridge complier result success but
the program that call external backend not working, probably I must rebuild also all backend with
same options flags aligned.

for the Icc & 4.7 coexisting ... (4.6.2 not this problem)

/usr/include/c++/4.7/ext/atomicity.h(48): error: identifier "__ATOMIC_ACQ_REL" is undefined
{ return __atomic_fetch_add(__mem, __val, __ATOMIC_ACQ_REL); }

root@debian-bustaf:/usr/bin# icc -v
icc version 12.1.0 (gcc version 4.6.0 compatibility)

root@debian-bustaf:/usr/bin# g++ -v
Using built-in specs.
Target: x86_64-linux-gnu
Configured with: ./configure --enable-languages=c,c++,fortran,objc,obj-c++ --prefix=/usr --program-suffix=-4.7 --enable-shared --enable-multiarch --enable-linker-build-id --with-system-zlib --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --with-gxx-include-dir=/usr/include/c++/4.7 --libdir=/usr/lib --enable-nls --enable-lto --with-ppl --with-mpfr --with-mpc --with-cloog --enable-cloog-backend=isl --enable-clocale=gnu --enable-libstdcxx-debug --enable-objc-gc --with-arch-32=i586 --with-tune=generic --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=x86_64-linux-gnu
Thread model: posix
gcc version 4.7.0 20120302 (prerelease) (GCC)


I submitted a premier issue (659938) on the incompatibility between g++ 4.7 atomicity.h and icpc 5 weeks ago. It was accepted as a feature request, with no indication of when it might be considered.
According to past history, I would not count on the problem being solved until there is a SLES, Ubuntu, or RHEL release using gcc 4.7 or 4.8 which would available for development of a future icpc release. So we would be stuck with removing current gcc from PATH, up through icc 13.0.
The efforts which have gone into making gcc more effective on current Intel platforms conflict with the use of Intel C++ until this problem is solved.
In my version of Levine-Callahan-Dongarra vectors test suite, under what I consider reasonable ground rules, g++ 4.7 out-performs icpc 12.1.3, on Westmere. It's necessary to update with all the special icpc pragmas in order to pull ahead.

Hi, thank for your informations

It's no problem for me, I can wait the future upgrade..
the rule to multiple path for get around the ICC problem header is the link (ln) version compiler
name complete (/usr/bin/g++-4.7) to short name g++ reflecting (cc) link.
I link dynamically g++-4.6.2 to g++ ( or with an loader using putenv(...)) temporary for having header
are correct to ICC.
Same, the Cloud Sandy Bridge machine using only one instance ,will able serving the two compilers...
(Better that nothing with preserving ICC before an upgrade could be better aligned)

(up through icc 13.0) more prudent is jumps directly 14.0 that is harmless number, all difficulty
existing already sufficing ....


I extend other tests...
I think wrong way to use -march-core-avx-i (the diy for anticipate an compatibility binary with IVY )
to Sandy Bridge..
Apache 2.4 (with apr, pcre etc ..) compile success but when started detected Illegal instruction with this flag.
But without this flag specific persisting largely improved with this new version and also GNU compiler 4.7 ..
An jewel ...
compile Apache 2.4 pass success also with ICC with well results

Best Reply

If you're asking whether the gcc Ivy Bridge option would generate instructions not supported on Sandy Bridge, you should be checking the gcc source code or asking on the gcc-help mail list. Setting -march for Sandy Bridge and -mtune for IVB should be OK. This may make more use of 256-bit wide loads, which would be slower if not aligned on Sandy Bridge.

Hi, thanks for your answers
(Setting -march for Sandy Bridge and -mtune for IVB should be OK)

Yes it work , I have make an control with large charge using (ab and also real) it
seem tuned is yet more effective

I have test an new build apr-1.4.6 & apr-util-1.4.1 with 2 flags IVY before an new build Apache 2.4
just when lib apr compiled with 2 flags Ivy apache give fault Illegal instruction.
I am already happy like that , In my life I never had a performance equaled like that with
using machine model range not very expensive.
Also congratulations Team apache, 2.4 is an fabulous result
when I have time i see source Gnu compiler particularity of (core-avx-i) but I'm afraid it 's too
complex for my old head now ...
Thanks lot


After an investigation more precise , it seem that problem AVX is specific to my
configuration used with my multiple complex backend API linked APACHE .
I think march avx for Ivy and Sandy are compatible with the Chipsets Intel Z68,Intel Z77.

the length you could scroll for read all lines Gnu compiler linked flag architecture almost equivalent
to one or two roll of toilet paper , never yet used ..
It takes courage and the willingness deepen its knowledges for load this type specific task
I think march and mtune require always are same value for avoid objectively, placebo effect ....
but flag -mrdrnd ,him,seem really very effective.
When I find an empty box with a PSU I will try with another mother board that use chipset Z77.

The other site does not answer anything to my request...
but not important now and thank all the same for link , some other subjects ,remain
interesting, also i have ,already resolved all alone the code source modification
for the video more optimized.

gcc offers both march and mtune in order to permit some optimization for newer architectures while excluding instructions which don't work on the newer architectures. For example, many people are still using versions of gcc without specific support for corei7, so might use -mtune=barcelona -ftree-vectorize to get good performance on current CPUs, Intel as well as AMD. icc had such options at one time but dropped them when the multiple architecture code path options were introduced.
A few days ago you wanted to generate code optimized for Ivy Bridge and run it on Sandy Bridge, which would exclude use of the additional IVB instructions. As you commented, it's entirely normal with either compiler to generate code targeted for the instruction set you're running on and forgo any optimizations for a future CPU. It may even be doubted whether a dual path build with both SNB and IVB would offer a net advantage over plain SNB code. I checked some of my own benchmarks with the current Intel compiler and found that the core-avx-i option did not widen any operations to avx-256 where the avx option chooses avx-128, and avx2 chooses avx-256. The compiler would not make separate avx and avx-i code paths for this purpose even if requested to do so.


I have perfectly understand, for me essential is it works if is possible ,and use is passive when
it's incorrect.
When require more precise now with speed build (-fwhole-program) i can build contextual
dynamically in real time some parts delicate.
The essential for me, i know now that results (2 Gen) compared to old model is same you move from
the dark night to light of day .... results significant evident and visible easily , for customers...

I forget ...

(have you an flag AVX to the customers pay more prompt ?)


About i have write precedent ..
(When I find an empty box with a PSU I will try with another mother board that
use chipset Z77.)

Mother board Chipset Z77 work well also with Sandy, but I wait Ivy processor before
rebuild all major packages Linux ... to confirm if is really result between 25 to 35%
better compared similar same frequency Sandy...
For me all benchmarks existing with games have not really value to the side where is I wait .

That I know is the price of this mother card him mount more than than 35% compared Z68,
is confirmed, It's sure .. Grrrrrrrrrrrrrr ... !!!!!

(If you add the price for new (pci) SSD 910 for speed the storage maybe It could result
sale with great success in Beverly Hills ... ( only during the tourist season) I think ...

Maybe more effective and realist is inserted default on mother board 10 / 15 Go only this
type of SSD , for hosting O/S system very accelerated , with a reasonable extra cost,
this for participate to a new life of PC machine traditional that is dying now with a
lack of innovation relevant.

If is true that SSD 910 could 2Go /s read sequential and 1 Go/s write sequential.
the results will improved largely , more evident that using only the head with
flags options relation to comportment compilator..

The news give announcement an approximative value

Intel SSD 910 400 to 800 Go
Price start 1930 $ to 3860 $

(the storage more expensive than a camel with five legs and three
bumps equipped valve.)

If I am refering
4.825 $ price to 1 Go
4.825 * 15 = 72.375 $

Even up to $ 200 still acceptable for 15 Go is an option
on mother board for hosting operating system.
it could be an recent object not exclusive reserved to large server
than only small number of people have access.

Also,80 Go only would suffice to me for help the side indexing
temporary with large database (mainframe)and used a chunk
dedicaced to partition swap.
He help also for catastropic time are required with large size program
when IPO option used.

It could be well if one user have already this object of luxury ,for
make an test with operating system,
we see if it's truly is effective or it's a utopia..

I have find the datasheet

Status Launched
Launch Date Q2'12
Sequential Read 1000 MB/s
Sequential Write 750 MB/s
Random Read (100% Span) 90000 IOPS
Random Write (100% Span) 38000 IOPS
Latency - Read 65 s
Latency - Write 65 s
Power - Active <25W
Power - Idle 8W
Weight 125g
Endurance Rating (Lifetime Writes) 7 PB
Warranty Period 5 yrs
Package Specifications
Capacity 400 GB
Form Factor 1/2 Height PCIe
Interface PCIe 2.0 X8
Lithography 25 nm
Advanced Technologies


I discover that 400 Go have half performance that 800 Go ....
I don't how many it will result for my poor 15 Go than I hope existing
one day....


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