Hi, I was testing code on my laptop a 32bit Duo core system and when i ran the same code on a 64bit system Duo core2
the program runs but it gives me wrong program output.When i trace thru the code i found that when the image im suppose to process hits the block with assembly code in it the processed image becomes blank i verified it with the same code running on my laptop the output is totally different. It works on a duo core system but on the 64bit duo core2 it doesnt work why is this so?
Im compiling my code on a 32 bit duo core system, running on ubuntu 7.10. The C++ code consists of
SIMD, inline assembly and SSE2 instructions.
What i found in intel website
Intel C++ Compiler
Is inline assembly supported?
Inline assembly is only supported by theIA-32
and Intel 64 C++ compilers (icc and icpc). GNU gas* and Microsoft
MASM* formats are available. There is no support for inline assembly on
the IA-64 architecture.
Does this mean code with inline assembly cannot run on 64bit systems?
Anyone has any idea what happened?
theres also this which i found in the documents for duo 2 processors What does the below mean when they talk about TLBS does it affect the way programs work?
Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS)
Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) of the
Intel 64 and IA-32 Architecture Software Developers Manual, Volume 3A: System
Programming Guide will be modified to include the presence of page table structure
caches, such as the page directory cache, which Intel processors implement. This
information is needed to aid operating systems in managing page table structure
Intel will update the Intel 64 and IA-32 Architecture Software Developers Manual,
Volume 3A: System Programming Guide in the coming months. Until that time, an
application note, TLBs, Paging-Structure Caches, and Their Invalidation
(http://www.intel.com/products/processor/manuals/index.htm) is available which
provides more information on the paging structure caches and TLB invalidation.
In rare instances, improper TLB invalidation may result in unpredictable system
behavior, such as system hangs or incorrect data. Developers of operating systems
should take this documentation into account when designing TLB invalidation
algorithms. For the processors affected, Intel has provided a recommended update to
system and BIOS vendors to incorporate into their BIOS to resolve this issue.