Hi Forum people,

this is an IA32 architecture question for performance, but I am not sure which would be a suitable forum for it, so I post is here.

It's about the balance of spatial locality of loads versus writes: I have a dilemma in my algorithm implementation: I could improve storage spatial locality at the expense of sacrifying loads spatial locality, but I don't know *how much* or any quantitative criteria, in the form of byte quantities.

I think that indeed spatial locality in storages is more important -in terms of performance- than spatial locality in loads, in order to decrease WCB partial evictions. However, I don't know where the limit is.

For example, an extreme would be ~100% of consecutive stores, but very 'spotted' (~0% consecutive) loads.

Do you know where/how I can determine such balance?

As input parameters of this criteria, I know:

- the number and size of the WCBs (from the pentium model; let's say Nwd)

- the cache parameters (L1 and L2 sizes, cache line size, etc.)

I would expect something like

optimum ratio: [load transaction size] VERSUS [storage transaction size]

Thanks!

daniel.