Changing Memory Initialization module

I was able to change the parameters. Thanks!

What about the SPD data. In my current BIOS I have to provide the following parameter array.

typedef struct {
  CONST UINT8   SpdPresent;
  CONST UINT8   MemType;
  CONST UINT8   MemModuleType;
  CONST UINT8   SdramDensityBanks;
  CONST UINT8   SdramAddressing;
  CONST UINT8   NomVoltage;
  CONST UINT8   ModOrganization;
  CONST UINT8   ModMemBusWidth;
  CONST UINT8   FineTimebaseDividend;
  CONST UINT8   MedTimebaseDividend;
  CONST UINT8   MedTimebaseDivisor;
  CONST UINT8   MinCycleTime;
  CONST UINT8   Rsrvd1;
  CONST UINT8   CASLatenciesLsb;
  CONST UINT8   CASLatenciesMsb;
  CONST UINT8   MinCASLatencyTime;
  CONST UINT8   MinWriteRecoveryTime;
  CONST UINT8   MinRASToCASDelayTime;
  CONST UINT8   MinRowActiveDelayTime;
  CONST UINT8   MinRowPrechargeDelayTime;
  CONST UINT8   UpperNibblesForRASAndRC;
  CONST UINT8   MinActiveToPrechargeDelayTime;
  CONST UINT8   MinActiveToRefreshDelayTime;
  CONST UINT8   MinRefreshRecoveryDelayTimeLsb;
  CONST UINT8   MinRefreshRecoveryDelayTimeMsb;
  CONST UINT8   MinWriteToReadCommandDelay;
  CONST UINT8   MinReadToPrechargeCommandDelay;
  CONST UINT8   UpperNibbleTfaw;
  CONST UINT8   MinFourActivateWindowDelay;
  CONST UINT8   OptionalFeatures;
  CONST UINT8   ThermalAndRefreshOptions;
  CONST UINT8   ModThermalSensor;
  CONST UINT8   DeviceType;
  CONST UINT8   rsrvd2[26];
  CONST UINT8   ModTypeSpecificSection[57];
  CONST UINT8   ModJedecIdCode[2];
  CONST UINT8   ModManufacturingLocation;
  CONST UINT8   ModManufacturingDate[2];
  CONST UINT8   ModSerialNumber[4];
  CONST UINT8   CRC[2];
} OEM_MRC_DIMM_MATRIX;

I added the custom memory parameters we require, and the board will boot up to Port 80 code 0x2F which is at the end of the memory initialization sequence (function SetInitDone I believe). Any idea why I could be freezing at this point?

Another question: Is dual-core the only version of Bay Trail supported?

Using an emulator, I was able to determine that the memory initialization was using the Fast Boot Path (FBPath). I built the BIOS with Fast Boot disabled, and it now took the S5 Path (S5Path) for memory initialization. It still stops booting at code 012Fh. Since this is the last step of the memory init sequence, I don't know if I have completed the init and locked up at the next BIOS step. What BIOS function is immediately after the memory init? 

It looks like I am stuck in a loop where the BIOS is trying to communicate with a serial port at address 3F8h. Am I required to have a serial port at this address? How can I disable this feature?

I deleted the UART with no luck. Still stops at 012Fh.

Unfortunately our UART ports go through a Lattice FPGA which defaults to disabled. I can generate a custom programming file that enables one of the ports at 3F8h. Is there any sort of USB debug port provided?

We have a custom SBC based on the Bay Trail processor that uses an in-house BIOS based on the Phoneix Secure-Core Technology version 3.1. The memory settings I am using are from that BIOS. Here are the settings I am using in the Firmware Engine:

  // hardcode values for C407 DDR3L memdown
  Input_Struct.Rank_En[0][0] = 1;          /**<  [Channel][Rank] Ranks Present with MAX_RANKS defined in Imemory.h */
  Input_Struct.Rank_En[0][1] = 0;          /**<  [Channel][Rank] Ranks Present with MAX_RANKS defined in Imemory.h */
  Input_Struct.Rank_En[1][0] = 0;          /**<  [Channel][Rank] Ranks Present with MAX_RANKS defined in Imemory.h */
  Input_Struct.Rank_En[1][1] = 0;          /**<  [Channel][Rank] Ranks Present with MAX_RANKS defined in Imemory.h */
  Input_Struct.DIMM_DWidth[0][0] = 0x1;    /**<  [Channel][Slot] DIMM0 DRAM device data width 00:x8, 01:x16, 02:x32*/
  Input_Struct.DIMM_Density[0][0] = 0x2;   /**< [Channel][Slot] DIMM0 DRAM device data density  00:1Gbit, 01:2Gbit,02:4Gbit,03:8Gbit*/
  Input_Struct.DRAM_Speed = 0x1;           /**< 00:800, 01:1066, 02:1333, 03:1600 */ 
  Input_Struct.DRAM_Type = 0x1;            /**< 00:DDR3, 01:DDR3L, 02:DDR3U, 04:LPDDR2, 05:LPDDR3, 06:DDR4 */ 
  Input_Struct.DIMM_MemDown = 0x1;         /**< 0:DIMM, 1:Memory Down */    
  Input_Struct.DIMM_BusWidth[0][0] = 3;    /**< [Channel][Slot] 000:8 bits; 01:16bits, 02:32bits, 03:64bits */
  Input_Struct.DIMM_Sides[0][0] = 0;       /**< [Channel][Slot] ranks per dimm 00:1rank, 01:2ranks, 02:3ranks, 03:4ranks */
  Input_Struct.tCL = 7;                    /**< actual CL */
  Input_Struct.tRP_tRCD = 7;               /**< TRP and tRCD in dram clk - 5:12.5ns, 6:15ns, 7:*/
  Input_Struct.tWR = 8;                    /**< in dram clk  */
  Input_Struct.tWTR = 4;                   /**< in dram clk  */
  Input_Struct.tRRD = 4;                   /**< in dram clk  */
  Input_Struct.tRTP = 4;                   /**< in dram clk  */
  Input_Struct.tFAW = 20;
 

Thanks for the assistance. I disabled all of the debug options since I never get any data on my console.

I agree that I am getting past the memory initialization code. Using the emulator, I can confirm that plenty of code is being executed after the memory init and that no further port 80 writes occur.

So why is my boot still freezing? I eventually stop at a halt instruction. I never get any video output on a VGA or Display Port monitor. I have added both monitor types to the component diagram. Why do they attach to the HDMI box?

After comparing schematics for the two boards, we are using different UART ports so I do not believe this will ever work. Our UART1 at 3F8h is on a programmable device connected to the LPC bus. I do not see any way I can add the console to the LPC block.

If I disable the console and debugging, the BIOS does not lock up in a UART loop but still does not boot. It runs until it executes a halt instruction.

Our board uses a E3825 processor and a Numonyx N25Q064A11 flash device.