Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Postsort ascending
Sticky topic Sticky: Links to instruction documentation
by Thomas Willhalm...
Fri, 12/31/2010 - 07:07 35
by james l.
Sun, 03/19/2017 - 15:43
Sticky topic Sticky: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
by Roman Dementiev...
Fri, 06/07/2013 - 06:46 6
by D. Hugh R.
Sat, 05/21/2016 - 09:28
Sticky topic Sticky: Intel® Software Development Emulator release 7.30
by Mark Charney (Intel)
Mon, 09/21/2015 - 05:23 3
by Sergio J. C.
Wed, 12/16/2015 - 12:26
Normal topic Intrinsic functions _rdtsc and _rdtscp
by Intel C.
Mon, 08/13/2018 - 10:56 2
by McCalpin, John
Tue, 08/14/2018 - 12:02
Hot topic Intel® Xeon Phi™ x200 series (KNL) Ring 3 Monitor/MWait
by Cownie, James H...
Thu, 10/13/2016 - 02:04 20
by Zihan Y.
Wed, 08/08/2018 - 19:17
Normal topic MWAIT is not improving performance and why my machine stucks?
by Zihan Y.
Fri, 08/03/2018 - 02:14 2
by Zihan Y.
Wed, 08/08/2018 - 00:38
Hot topic Bugs in Intrinsics Guide (Page: 1, 2, 3, 4)
by andysem
Wed, 01/30/2013 - 00:24 167
by Jin, Wz
Thu, 07/26/2018 - 01:05
Normal topic When will SnowRidge be available?
by Zihan Y.
Sun, 07/22/2018 - 19:16 2
by Zihan Y.
Tue, 07/24/2018 - 06:30
Normal topic RDTSC to measure performance of small # of FP calculations
by Drum, Anthony
Fri, 07/20/2018 - 03:48 2
by Drum, Anthony
Mon, 07/23/2018 - 08:25
Normal topic I understand Why SSE is slower than ANSI C
by Yavorski, Nick
Thu, 07/19/2018 - 03:52 0
by Yavorski, Nick
Thu, 07/19/2018 - 03:52
Normal topic Using AVX opcodes slow my proc
by Dmk Z.
Fri, 06/08/2018 - 08:34 2
by Dmk Z.
Fri, 07/13/2018 - 07:53
Normal topic State of AVX 512 on Skylake-X
by jan v.
Sat, 07/08/2017 - 02:17 10
by jan v.
Tue, 07/03/2018 - 08:54
Normal topic Error in pseudo-code for RDPMC in SWDM Volume 2
by McCalpin, John
Tue, 06/19/2018 - 08:33 5
by McCalpin, John
Fri, 06/22/2018 - 11:19
Normal topic what are the performance implications of using vmovups and vmovapd instructions respectively?
by Aketh T.
Wed, 06/20/2018 - 13:22 1
by McCalpin, John
Thu, 06/21/2018 - 09:20
Normal topic Confusion in behavior of _mm256_loadu_ps and _mm256_loadu_ps instrinsics
by Aketh T.
Thu, 06/21/2018 - 07:05 1
by McCalpin, John
Thu, 06/21/2018 - 09:05
Normal topic AVX-512 release date
by いらきゅ
Sun, 06/03/2018 - 21:56 4
by いらきゅ
Sat, 06/16/2018 - 12:19
Normal topic KUNPCK* instructions behavior in SDM and Intrinsics Guide
by andysem
Thu, 06/14/2018 - 17:08 1
by Mark Charney (Intel)
Fri, 06/15/2018 - 05:31
Normal topic gcc not finding a _mm256_storeu2_m128i
by rajathadripura ...
Wed, 06/06/2018 - 07:10 1
by Richard Nutman
Fri, 06/08/2018 - 05:04
Normal topic LDDQU vs. MOVDQU guidelines
by andysem
Thu, 05/03/2018 - 09:59 9
by Travis D.
Tue, 05/15/2018 - 21:03
Normal topic The memory ordering semantics of mfence versus those of locked instructions
by Travis D.
Wed, 05/09/2018 - 20:51 1
by McCalpin, John
Thu, 05/10/2018 - 11:12
Normal topic Support for saturation and addition instruction in AVX-512
by Udupi, Nagacharan
Mon, 03/19/2018 - 12:39 1
by Christopher H.
Sun, 05/06/2018 - 01:01
Normal topic What is the status of VZEROUPPER use?
by Agner
Fri, 11/25/2016 - 12:22 12
by Agner
Mon, 04/23/2018 - 10:32
Normal topic Enabling Mon feature using IA32_MISC_ENABLES
by K., Sina
Mon, 04/09/2018 - 23:24 0
by K., Sina
Mon, 04/09/2018 - 23:24
Normal topic Possible errors in instruction semantics
by Dasgupta, Sandeep
Wed, 04/04/2018 - 17:48 4
by Dasgupta, Sandeep
Thu, 04/05/2018 - 13:36
Normal topic Update the SDE MSVS debugger install kit to support VS2017?
by Ens, John
Fri, 12/22/2017 - 07:40 1
by Ady Tal (Intel)
Sat, 03/31/2018 - 23:56
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For more complete information about compiler optimizations, see our Optimization Notice.