Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
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Topic / Topic starter Post date Replies Last Postsort ascending
Sticky topic Sticky: Links to instruction documentation
by Thomas Willhalm... 		Fri, 12/31/2010 - 07:07 35
 by james l.
Sun, 03/19/2017 - 15:43
Sticky topic Sticky: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
by Roman Dementiev... 		Fri, 06/07/2013 - 06:46 6
 by D. Hugh R.
Sat, 05/21/2016 - 09:28
Sticky topic Sticky: Intel® Software Development Emulator release 7.30
by Mark Charney (Intel) 		Mon, 09/21/2015 - 05:23 3
 by Sergio J. C.
Wed, 12/16/2015 - 12:26
Normal topic Transpose for 4x4 Matrix(double)
by Shaquille W. 		Sat, 10/21/2017 - 23:03 1
 by McCalpin, John
Mon, 10/23/2017 - 14:12
Normal topic Where is _mm512_i32extgather_epi32 defined?
by Henk-Jan L. 		Thu, 10/05/2017 - 07:44 1
 by Mathieu Gravey
Mon, 10/23/2017 - 13:36
Normal topic Complex multiply–accumulate
by Mathieu Gravey 		Mon, 10/23/2017 - 10:12 0
 by Mathieu Gravey
Mon, 10/23/2017 - 10:12
Normal topic Understanding Bitwise Intrinsics
by Yash Akhauri 		Fri, 10/20/2017 - 02:43 1
 by andysem
Fri, 10/20/2017 - 15:40
Normal topic #SS on inter-privilege IRET
by Konstantin B. 		Sat, 07/15/2017 - 00:44 2
 by jimdempseyatthecove
Thu, 10/19/2017 - 09:26
Normal topic Running _mm512_popcnt_epi32 on colfax using icc?
by Yash Akhauri 		Thu, 10/19/2017 - 05:20 5
 by Yash Akhauri
Thu, 10/19/2017 - 08:26
Normal topic Does Non-Temporal Load/Store Hints have different behavior for WC, WB memory type?
by Louis 		Thu, 10/19/2017 - 00:39 0
 by Louis
Thu, 10/19/2017 - 00:39
Normal topic Which processor families support RDPID instruction?
by David Y. 		Mon, 10/02/2017 - 11:39 2
 by David Y.
Tue, 10/03/2017 - 13:26
Normal topic Why AVX code slower then native C++ code ?
by Jorn V. 		Sat, 09/30/2017 - 03:49 1
 by Cownie, James H...
Mon, 10/02/2017 - 01:56
Normal topic Costs of scatter store
by Johannes P. 		Mon, 09/04/2017 - 11:28 2
 by Anil M.
Sat, 09/30/2017 - 04:29
Normal topic Check arrays for equality with SIMD
by CommanderLake 		Thu, 09/14/2017 - 10:28 4
 by Anil M.
Sat, 09/30/2017 - 03:17
Hot topic Why is Intel allowing this?!?
by Igor Levicki 		Fri, 04/14/2017 - 17:01 33
 by Igor Levicki
Mon, 09/25/2017 - 14:52
Normal topic Binary operations per clock cycle in Intel Xeon Phi processors.
by Yash Akhauri 		Fri, 09/22/2017 - 08:51 3
 by jimdempseyatthecove
Mon, 09/25/2017 - 10:47
Hot topic Bugs in Intrinsics Guide (Page: 1, 2, 3, 4)
by andysem 		Wed, 01/30/2013 - 00:24 152
 by Gregg S. (Intel)
Thu, 09/21/2017 - 15:02
Hot topic AVX512f on non-MIC this year?
by angus-hewlett 		Fri, 01/30/2015 - 02:56 16
 by jimdempseyatthecove
Sun, 09/17/2017 - 11:12
Normal topic Pin tool AVX scalar/vector identification
by Marko S. 		Fri, 09/08/2017 - 08:24 3
 by Mark Charney (Intel)
Mon, 09/11/2017 - 13:01
Normal topic How to change Intel BIOS Settings
by webdesigncompany 		Sun, 09/10/2017 - 01:33 0
 by webdesigncompany
Sun, 09/10/2017 - 01:33
Normal topic State of AVX 512 on Skylake-X
by jan v. 		Sat, 07/08/2017 - 02:17 8
 by jan v.
Thu, 09/07/2017 - 09:02
Normal topic Software Development Emulator for Windows XP
by Adam L. 		Wed, 08/09/2017 - 06:24 2
 by Adam L.
Fri, 09/01/2017 - 03:13
Normal topic Using scatterstore to interleave two (sparse) 512-bit vector registers
by Johannes P. 		Thu, 08/24/2017 - 03:29 1
 by jimdempseyatthecove
Fri, 08/25/2017 - 07:53
Normal topic New instruction proposal: memcmp-like int compare
by Daniel F. 		Sat, 08/19/2017 - 20:52 13
 by Daniel F.
Tue, 08/22/2017 - 11:12
Normal topic AVX-512 tzcnt
by Johannes P. 		Sun, 08/20/2017 - 07:22 1
 by andysem
Tue, 08/22/2017 - 09:43
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For more complete information about compiler optimizations, see our Optimization Notice.