Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Postsort ascending
Sticky topic Sticky: Links to instruction documentation
by Thomas Willhalm...
Fri, 12/31/2010 - 07:07 35
by james l.
Sun, 03/19/2017 - 15:43
Sticky topic Sticky: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
by Roman Dementiev...
Fri, 06/07/2013 - 06:46 6
by D. Hugh R.
Sat, 05/21/2016 - 09:28
Sticky topic Sticky: Intel® Software Development Emulator release 7.30
by Mark Charney (Intel)
Mon, 09/21/2015 - 05:23 3
by Sergio J. C.
Wed, 12/16/2015 - 12:26
Normal topic Vectorization - Speed up expected for SSE and AVX
by henry petit
Thu, 04/27/2017 - 06:30 3
by Igor Levicki
Sat, 04/29/2017 - 08:31
Hot topic Why is Intel allowing this?!?
by Igor Levicki
Fri, 04/14/2017 - 17:01 29
by Igor Levicki
Sat, 04/29/2017 - 07:03
Normal topic Data source for intrinsics guide
by Evan N.
Mon, 04/24/2017 - 19:28 13
by Sergey Kostrov
Wed, 04/26/2017 - 07:42
Normal topic List of interrupss
by Joseph Reichman
Sun, 04/23/2017 - 09:36 2
by Sergey Kostrov
Tue, 04/25/2017 - 09:39
Normal topic RTM/HLE abort while write to X87 control-word?
by Oliver K.
Mon, 04/03/2017 - 02:47 4
by Oliver K.
Mon, 04/24/2017 - 00:30
Normal topic Is PTWRITE and POWERSTAT Packets supported on 7th core processor?
by claw L.
Thu, 04/20/2017 - 08:53 3
by gaston-hillar
Thu, 04/20/2017 - 20:22
Normal topic meaning of RTM abort status
by Oliver K.
Thu, 04/13/2017 - 04:45 2
by andysem
Sun, 04/16/2017 - 16:50
Normal topic QPI will abort TSX transactions?
by Oliver K.
Sat, 04/15/2017 - 22:28 0
by Oliver K.
Sat, 04/15/2017 - 22:28
Normal topic RTM abort status 'RETRY'?
by Oliver K.
Thu, 04/13/2017 - 01:53 2
by Oliver K.
Thu, 04/13/2017 - 05:16
Normal topic RTM/HLE abort on stack pointer mod
by Oliver K.
Mon, 04/03/2017 - 02:24 5
by Cownie, James H
Tue, 04/04/2017 - 05:43
Normal topic SDE ERROR: Cannot execute XGETBV with ECX != 0
by Vaclav L.
Fri, 03/10/2017 - 09:01 3
by Ady Tal (Intel)
Mon, 04/03/2017 - 22:57
Normal topic best practice for evaluating AVX2 vs SSE4 parallel task power?
by Todd West
Mon, 03/27/2017 - 17:49 8
by jimdempseyatthecove
Mon, 04/03/2017 - 17:19
Normal topic cache adressed
by Rafał B.
Fri, 03/24/2017 - 18:11 1
by gaston-hillar
Sun, 04/02/2017 - 20:17
Normal topic Cache L1 , L2 , L3 ?
by Rafał B.
Tue, 03/07/2017 - 10:59 3
by gaston-hillar
Sun, 04/02/2017 - 19:58
Normal topic AVX in SGX
by Arya Pourtabatabaie
Fri, 02/24/2017 - 09:07 1
by gaston-hillar
Fri, 03/31/2017 - 21:09
Normal topic E-class CPUs down clock when AVX is in the execution stack? Is this true, if so why would it?
by steve s.
Tue, 03/21/2017 - 00:27 3
by steve s.
Fri, 03/24/2017 - 22:14
Hot topic It is Not possible to run latest versions of SDE, for example 7.49.0, on 32-bit Windows platforms
by Sergey Kostrov
Mon, 03/06/2017 - 09:43 22
by Sergey Kostrov
Wed, 03/22/2017 - 14:40
Normal topic i5-3210 M 2,5 GHz and 2xE5 2609 2,4 GHz datas
by Rafał B.
Fri, 03/03/2017 - 14:45 2
by Sergey Kostrov
Mon, 03/06/2017 - 10:58
Normal topic Will access and checks through segment register incur more overhead?
by claw L.
Sun, 03/05/2017 - 16:54 2
by Sergey Kostrov
Mon, 03/06/2017 - 10:07
Normal topic madvise
by Rafał B.
Fri, 03/03/2017 - 11:30 0
by Rafał B.
Fri, 03/03/2017 - 11:30
Hot topic Bugs in Intrinsics Guide (Page: 1, 2, 3)
by andysem
Wed, 01/30/2013 - 00:24 147
by andysem
Fri, 03/03/2017 - 04:27
Normal topic what type of NMI can trigger VMX NMI exiting
by Tao W.
Thu, 02/16/2017 - 20:39 3
by Tao W.
Wed, 03/01/2017 - 00:37
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.