Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Postsort ascending
Sticky topic Sticky: Links to instruction documentation
by Thomas Willhalm...
Fri, 12/31/2010 - 07:07 35
by james l.
Sun, 03/19/2017 - 15:43
Sticky topic Sticky: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
by Roman Dementiev...
Fri, 06/07/2013 - 06:46 6
by D. Hugh R.
Sat, 05/21/2016 - 09:28
Sticky topic Sticky: Intel® Software Development Emulator release 7.30
by Mark Charney (Intel)
Mon, 09/21/2015 - 05:23 3
by Sergio J. C.
Wed, 12/16/2015 - 12:26
Normal topic E-class CPUs down clock when AVX is in the execution stack? Is this true, if so why would it?
by steve s.
Tue, 03/21/2017 - 00:27 2
by IAN S.
Thu, 03/23/2017 - 11:59
Hot topic It is Not possible to run latest versions of SDE, for example 7.49.0, on 32-bit Windows platforms
by Sergey Kostrov
Mon, 03/06/2017 - 09:43 22
by Sergey Kostrov
Wed, 03/22/2017 - 14:40
Normal topic SDE ERROR: Cannot execute XGETBV with ECX != 0
by Vaclav L.
Fri, 03/10/2017 - 09:01 1
by Ady Tal (Intel)
Sat, 03/11/2017 - 22:54
Normal topic Cache L1 , L2 , L3 ?
by Rafał B.
Tue, 03/07/2017 - 10:59 1
by jimdempseyatthecove
Tue, 03/07/2017 - 14:05
Normal topic i5-3210 M 2,5 GHz and 2xE5 2609 2,4 GHz datas
by Rafał B.
Fri, 03/03/2017 - 14:45 2
by Sergey Kostrov
Mon, 03/06/2017 - 10:58
Normal topic Will access and checks through segment register incur more overhead?
by claw L.
Sun, 03/05/2017 - 16:54 2
by Sergey Kostrov
Mon, 03/06/2017 - 10:07
Normal topic madvise
by Rafał B.
Fri, 03/03/2017 - 11:30 0
by Rafał B.
Fri, 03/03/2017 - 11:30
Hot topic Bugs in Intrinsics Guide (Page: 1, 2, 3)
by andysem
Wed, 01/30/2013 - 00:24 147
by andysem
Fri, 03/03/2017 - 04:27
Normal topic what type of NMI can trigger VMX NMI exiting
by Tao W.
Thu, 02/16/2017 - 20:39 3
by Tao W.
Wed, 03/01/2017 - 00:37
Normal topic AVX in SGX
by Arya Pourtabatabaie
Fri, 02/24/2017 - 09:07 0
by Arya Pourtabatabaie
Fri, 02/24/2017 - 09:07
Hot topic Random slow downs with AVX2 code.
by Anil M.
Tue, 01/31/2017 - 16:40 31
by Ady Tal (Intel)
Thu, 02/23/2017 - 13:58
Normal topic Cannot access compiler intrinsics for logarithm in Visual Studio
by Anil M.
Wed, 01/25/2017 - 08:43 2
by Anil M.
Mon, 02/20/2017 - 21:50
Normal topic Parallelization + Vectorization using OpenMP in Sandy Bridge
by Claudia W.
Mon, 01/09/2017 - 00:05 2
by Alexander L.
Mon, 02/20/2017 - 07:07
Normal topic Supported processors for PTWRITE instruction?
by Muhammad Usman N.
Wed, 11/30/2016 - 11:37 2
by BEEMAN S.
Fri, 02/17/2017 - 12:50
Normal topic Skylake Xeon and AVX-512VL
by Martin Z.
Thu, 02/16/2017 - 00:28 3
by areid
Fri, 02/17/2017 - 00:22
Normal topic why is ‘_mm512d load/store’ intrinsic changed to vmovups not vmovupd?
by Yeongha L.
Sun, 02/12/2017 - 23:09 1
by McCalpin, John
Mon, 02/13/2017 - 09:29
Normal topic Question about latency
by Alexander L.
Sun, 01/29/2017 - 07:09 9
by Todd West
Sun, 02/12/2017 - 15:14
Normal topic Slightly OT, but maybe somebody has an idea.
by Alexander L.
Mon, 02/06/2017 - 16:11 7
by andysem
Tue, 02/07/2017 - 07:56
Normal topic Intel® Xeon Phi™ x200 series (KNL) Ring 3 Monitor/MWait
by Cownie, James H
Thu, 10/13/2016 - 02:04 8
by Cownie, James H
Mon, 02/06/2017 - 01:41
Normal topic Question about performance difference SSE4/AVX vs. AVX2 with dual-channel vs. quad-channel memory
by Alexander L.
Wed, 02/01/2017 - 16:43 4
by Alexander L.
Fri, 02/03/2017 - 14:23
Normal topic E5-1650 v4, What are the AVX 'Base and 'Turbo' Speeds?
by Gregory Bohn
Tue, 01/31/2017 - 18:04 3
by McCalpin, John
Thu, 02/02/2017 - 10:54
Normal topic Why FMA is slower than SSE here?
by Daniel F.
Fri, 12/16/2016 - 02:23 4
by McCalpin, John
Thu, 01/26/2017 - 13:23
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
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Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.