Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:
- Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
- Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
- Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
- Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
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Links to instruction documentation by Thomas Willhalm... |
Fri, 12/31/2010 - 07:07 |
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Resources about Intel® Transactional Synchronization Extensions (Intel TSX) by Roman Dementiev... |
Fri, 06/07/2013 - 06:46 |
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Intel® Software Development Emulator release 7.30 by Mark Charney (Intel) |
Mon, 09/21/2015 - 05:23 |
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What is the status of VZEROUPPER use? by Agner |
Fri, 11/25/2016 - 12:22 |
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Bugs in Intrinsics Guide
by andysem |
Wed, 01/30/2013 - 00:24 |
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Enabling Mon feature using IA32_MISC_ENABLES by K., Sina |
Mon, 04/09/2018 - 23:24 |
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Possible errors in instruction semantics by Dasgupta, Sandeep |
Wed, 04/04/2018 - 17:48 |
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Update the SDE MSVS debugger install kit to support VS2017? by Ens, John |
Fri, 12/22/2017 - 07:40 |
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Immediate operands for SSE instructions? by Luchezar B. |
Thu, 03/22/2018 - 08:48 |
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Why is Intel allowing this?!? by Igor Levicki |
Fri, 04/14/2017 - 17:01 |
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Vector processing needs better NAN propagation by Agner |
Mon, 03/19/2018 - 00:41 |
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Performance delays - programming with QNan and Denormals by zalia64 |
Tue, 03/13/2018 - 08:12 |
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Support for saturation and addition instruction in AVX-512 by Udupi, Nagacharan |
Mon, 03/19/2018 - 12:39 |
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How to get the FLOP number of an application? by zhang t. |
Fri, 03/02/2018 - 17:51 |
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Histogram examples using AVX-512 CD in Dec 2017 Optimization Ref Manual are wrong? by Nelson, Trent |
Thu, 03/01/2018 - 06:37 |
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How to Reduce CAL (Function Call Interrupts ) on x86_64 architectures in /proc/interrupts by Kumar, Satish |
Tue, 02/20/2018 - 00:00 |
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Convert bytes to nibbles by CommanderLake |
Tue, 11/07/2017 - 07:56 |
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Parallel dependence in bitmap scaling code by CommanderLake |
Sat, 02/03/2018 - 18:55 |
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If the frequency is set to the P_STATE 1, why AVX-512 is not running to its base frequency? by Jordi V. |
Tue, 01/23/2018 - 12:32 |
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AVX-512 VBMI2: why no vector version of _pext_u32()? by Mikkelsen, Morten |
Thu, 01/11/2018 - 16:24 |
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how to turn off out-of-order execution in Intel processor by ddmetro |
Sun, 10/25/2009 - 14:32 |
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AVX512-VBMI2: VPSHLDV masks its shift count preventing use as a blend by Peter Cordes |
Sat, 12/09/2017 - 12:23 |
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AVX512 missing intrinsics by Cloyz |
Sat, 11/25/2017 - 15:38 |
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SSE and AVX behavior with aligned/unaligned instructions by Mark D. |
Thu, 12/07/2017 - 14:17 |
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AVX512 auto-vectorization on i9-7900X by Marko S. |
Thu, 11/02/2017 - 11:50 |
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