Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
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Topic / Topic starter Post date Replies Last Postsort ascending
Sticky topic Sticky: Links to instruction documentation
by Thomas Willhalm... 		Fri, 12/31/2010 - 07:07 35
 by james l.
Sun, 03/19/2017 - 15:43
Sticky topic Sticky: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
by Roman Dementiev... 		Fri, 06/07/2013 - 06:46 6
 by D. Hugh R.
Sat, 05/21/2016 - 09:28
Sticky topic Sticky: Intel® Software Development Emulator release 7.30
by Mark Charney (Intel) 		Mon, 09/21/2015 - 05:23 3
 by Sergio J. C.
Wed, 12/16/2015 - 12:26
Normal topic LDDQU vs. MOVDQU guidelines
by andysem 		Thu, 05/03/2018 - 09:59 9
 by Travis D.
Tue, 05/15/2018 - 21:03
Normal topic The memory ordering semantics of mfence versus those of locked instructions
by Travis D. 		Wed, 05/09/2018 - 20:51 1
 by McCalpin, John
Thu, 05/10/2018 - 11:12
Normal topic Support for saturation and addition instruction in AVX-512
by Udupi, Nagacharan 		Mon, 03/19/2018 - 12:39 1
 by Christopher H.
Sun, 05/06/2018 - 01:01
Normal topic What is the status of VZEROUPPER use?
by Agner 		Fri, 11/25/2016 - 12:22 12
 by Agner
Mon, 04/23/2018 - 10:32
Hot topic Bugs in Intrinsics Guide (Page: 1, 2, 3, 4)
by andysem 		Wed, 01/30/2013 - 00:24 164
 by Matthias Kretz
Mon, 04/23/2018 - 01:40
Normal topic Enabling Mon feature using IA32_MISC_ENABLES
by K., Sina 		Mon, 04/09/2018 - 23:24 0
 by K., Sina
Mon, 04/09/2018 - 23:24
Normal topic Possible errors in instruction semantics
by Dasgupta, Sandeep 		Wed, 04/04/2018 - 17:48 4
 by Dasgupta, Sandeep
Thu, 04/05/2018 - 13:36
Normal topic Update the SDE MSVS debugger install kit to support VS2017?
by Ens, John 		Fri, 12/22/2017 - 07:40 1
 by Ady Tal (Intel)
Sat, 03/31/2018 - 23:56
Normal topic Immediate operands for SSE instructions?
by Luchezar B. 		Thu, 03/22/2018 - 08:48 0
 by Luchezar B.
Thu, 03/22/2018 - 08:48
Hot topic Why is Intel allowing this?!?
by Igor Levicki 		Fri, 04/14/2017 - 17:01 38
 by Igor Levicki
Wed, 03/21/2018 - 12:38
Normal topic Vector processing needs better NAN propagation
by Agner 		Mon, 03/19/2018 - 00:41 7
 by Agner
Tue, 03/20/2018 - 23:50
Normal topic Performance delays - programming with QNan and Denormals
by zalia64 		Tue, 03/13/2018 - 08:12 7
 by McCalpin, John
Tue, 03/20/2018 - 10:45
Normal topic How to get the FLOP number of an application?
by zhang t. 		Fri, 03/02/2018 - 17:51 9
 by jimdempseyatthecove
Tue, 03/13/2018 - 14:57
Normal topic Histogram examples using AVX-512 CD in Dec 2017 Optimization Ref Manual are wrong?
by Nelson, Trent 		Thu, 03/01/2018 - 06:37 6
 by Christopher H. ...
Sat, 03/03/2018 - 15:41
Normal topic How to Reduce CAL (Function Call Interrupts ) on x86_64 architectures in /proc/interrupts
by Kumar, Satish 		Tue, 02/20/2018 - 00:00 0
 by Kumar, Satish
Tue, 02/20/2018 - 00:00
Normal topic Convert bytes to nibbles
by CommanderLake 		Tue, 11/07/2017 - 07:56 3
 by Igor Levicki
Tue, 02/13/2018 - 10:21
Normal topic Parallel dependence in bitmap scaling code
by CommanderLake 		Sat, 02/03/2018 - 18:55 7
 by jimdempseyatthecove
Wed, 02/07/2018 - 05:26
Normal topic If the frequency is set to the P_STATE 1, why AVX-512 is not running to its base frequency?
by Jordi V. 		Tue, 01/23/2018 - 12:32 3
 by McCalpin, John
Thu, 01/25/2018 - 07:12
Normal topic AVX-512 VBMI2: why no vector version of _pext_u32()?
by Mikkelsen, Morten 		Thu, 01/11/2018 - 16:24 0
 by Mikkelsen, Morten
Thu, 01/11/2018 - 16:24
Normal topic how to turn off out-of-order execution in Intel processor
by ddmetro 		Sun, 10/25/2009 - 14:32 14
 by william l.
Wed, 01/03/2018 - 21:15
Normal topic AVX512-VBMI2: VPSHLDV masks its shift count preventing use as a blend
by Peter Cordes 		Sat, 12/09/2017 - 12:23 0
 by Peter Cordes
Sat, 12/09/2017 - 12:23
Normal topic AVX512 missing intrinsics
by Cloyz 		Sat, 11/25/2017 - 15:38 3
 by Peter Cordes
Sat, 12/09/2017 - 11:46
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For more complete information about compiler optimizations, see our Optimization Notice.