some instruction are decocded into more than one uops , such as memory operand arithmetic ,mulsd (%rsi,%rax,8), %xmm1 are decoded into one mov uop and one mul uop.
I wonder whether the two uop be issued at the same time ?
have a look at Intel 64 and IA-32 Architectures Optimization Reference Manualthere are chapters that describe details of decode step, like "18.104.22.168 Instruction Decode",for example, quote:The microsequencer can provide up to 3 ops per cycle, and helps decode instructions larger than 4 ops
it depends on what you mean by "issued" - they cannot be executed at the same time,as mul needs data to be loaded first by the load uop,it is the scheduler, aka RS(Reservation Station), that receives uops after the decode and is responsible for triggering uops to go to execution onceuop's sources are (or expected to be) ready.
I understand. Thank you, Max.