I'm working with Core2Duo (ICH8 as south bridge).
I want to do the following steps:
Step 1: Do some calculations,
Step 2: Arm the timer for few seconds
Step 3:Get into C4 using the following code.
Step 4: Get an interruptwhen thetimer reaches 0
Step 5: Go back to Step 1
The code used to move to C4 is:
mov EAX, 0x30 (Bits 0-3 define C4 sub state. What sub state shoud I use ?)
mov ECX, 0x0 (Should I use 0x1 ?)
When I ran cpuid with EAX=5I got:
Bit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported
Bit 01: Supports treating interrupts as break-event for MWAIT, even when interrupts disabled
Bits 03 - 00: Number of C0 sub C-states supported using MWAIT
Bits 07 - 04: Number of C1 sub C-states supported using MWAIT
Bits 11 - 08: Number of C2 sub C-states supported using MWAIT
Bits 15 - 12: Number of C3 sub C-states supported using MWAIT
Bits 19 - 16: Number of C4 sub C-states supported using MWAIT
So the timer I will use has to generate an interrupt after TBD seconds and also must keep working under C4.
Can you help ?