This is my first time posting here, sorry if this is in the wrong subforum.
To the best of my knowledge, TSX uses the L1 cache coherency protocol to monitor the read/write sets for a transaction. Something which I've been wondering for a while now is how would this scale to systems with >1 processors. I'm not familiar with how such systems maintain cache coherency at L1, but is it feasible for TSX to work correctly and efficiently in these kinds of systems?
Also, is this why the server variants of Haswell are only available for single socket systems?