Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic Popcount emulation for x64 process - RAM memory limit
by Jon D.
Tue, 05/23/2017 - 06:46 3
by Sergey Kostrov
Wed, 05/31/2017 - 08:55
Normal topic SDE ERROR: Cannot execute XGETBV with ECX != 0
by Vaclav L.
Fri, 03/10/2017 - 09:01 5
by David L.
Thu, 05/25/2017 - 10:13
Normal topic 3D X-Point programming versus OS context switching
by David Z.
Mon, 05/15/2017 - 10:14 6
by David Z.
Tue, 05/23/2017 - 15:34
Normal topic SSE/AVX/FMA Unexpected Test Results
by Samuel Š.
Wed, 05/10/2017 - 10:37 11
by Sergey Kostrov
Wed, 05/17/2017 - 12:38
Hot topic It is Not possible to run latest versions of SDE, for example 7.49.0, on 32-bit Windows platforms
by Sergey Kostrov
Mon, 03/06/2017 - 09:43 26
by Sergey Kostrov
Fri, 05/12/2017 - 13:25
Normal topic Calculate Miss rate of L2 cache given global and L1 miss rates
by Papote J.
Sun, 05/07/2017 - 12:54 0
by Papote J.
Sun, 05/07/2017 - 12:54
Hot topic Data source for intrinsics guide
by Evan N.
Mon, 04/24/2017 - 19:28 16
by Sergey Kostrov
Thu, 05/04/2017 - 14:51
Normal topic List of interrupss
by Joseph R.
Sun, 04/23/2017 - 09:36 2
by Sergey Kostrov
Tue, 04/25/2017 - 09:39
Normal topic RTM/HLE abort while write to X87 control-word?
by Oliver K.
Mon, 04/03/2017 - 02:47 4
by Oliver K.
Mon, 04/24/2017 - 00:30
Normal topic Is PTWRITE and POWERSTAT Packets supported on 7th core processor?
by claw L.
Thu, 04/20/2017 - 08:53 3
by gaston-hillar
Thu, 04/20/2017 - 20:22
Normal topic meaning of RTM abort status
by Oliver K.
Thu, 04/13/2017 - 04:45 2
by andysem
Sun, 04/16/2017 - 16:50
Normal topic QPI will abort TSX transactions?
by Oliver K.
Sat, 04/15/2017 - 22:28 0
by Oliver K.
Sat, 04/15/2017 - 22:28
Normal topic RTM abort status 'RETRY'?
by Oliver K.
Thu, 04/13/2017 - 01:53 2
by Oliver K.
Thu, 04/13/2017 - 05:16
Normal topic RTM/HLE abort on stack pointer mod
by Oliver K.
Mon, 04/03/2017 - 02:24 5
by Cownie, James H...
Tue, 04/04/2017 - 05:43
Normal topic best practice for evaluating AVX2 vs SSE4 parallel task power?
by Todd W.
Mon, 03/27/2017 - 17:49 8
by jimdempseyatthecove
Mon, 04/03/2017 - 17:19
Normal topic cache adressed
by Rafał B.
Fri, 03/24/2017 - 18:11 1
by gaston-hillar
Sun, 04/02/2017 - 20:17
Normal topic Cache L1 , L2 , L3 ?
by Rafał B.
Tue, 03/07/2017 - 10:59 3
by gaston-hillar
Sun, 04/02/2017 - 19:58
Normal topic AVX in SGX
by Arya P.
Fri, 02/24/2017 - 09:07 1
by gaston-hillar
Fri, 03/31/2017 - 21:09
Normal topic E-class CPUs down clock when AVX is in the execution stack? Is this true, if so why would it?
by steve s.
Tue, 03/21/2017 - 00:27 3
by steve s.
Fri, 03/24/2017 - 22:14
Normal topic i5-3210 M 2,5 GHz and 2xE5 2609 2,4 GHz datas
by Rafał B.
Fri, 03/03/2017 - 14:45 2
by Sergey Kostrov
Mon, 03/06/2017 - 10:58
Normal topic Will access and checks through segment register incur more overhead?
by claw L.
Sun, 03/05/2017 - 16:54 2
by Sergey Kostrov
Mon, 03/06/2017 - 10:07
Normal topic madvise
by Rafał B.
Fri, 03/03/2017 - 11:30 0
by Rafał B.
Fri, 03/03/2017 - 11:30
Normal topic what type of NMI can trigger VMX NMI exiting
by Tao W.
Thu, 02/16/2017 - 20:39 3
by Tao W.
Wed, 03/01/2017 - 00:37
Hot topic Random slow downs with AVX2 code.
by Anil M.
Tue, 01/31/2017 - 16:40 31
by Ady Tal (Intel)
Thu, 02/23/2017 - 13:58
Normal topic Cannot access compiler intrinsics for logarithm in Visual Studio
by Anil M.
Wed, 01/25/2017 - 08:43 2
by Anil M.
Mon, 02/20/2017 - 21:50
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For more complete information about compiler optimizations, see our Optimization Notice.