Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic code optimization and vtune
by Zhiyong Z.
Tue, 01/12/2016 - 14:03 8
by iliyapolak
Thu, 01/14/2016 - 09:51
Normal topic Intel TSX-NI with m3-6Y30 processor
by Jeremy W.
Wed, 01/06/2016 - 07:48 1
by Mark Charney (Intel)
Tue, 01/12/2016 - 14:13
Normal topic How to generate the SIGSTRUCT and EINITTOKEN for Intel SGX EINIT instruction?
by gu j.
Wed, 12/23/2015 - 02:46 3
by Simon Johnson (...
Mon, 01/04/2016 - 13:34
Normal topic Error code of einit
by gu j.
Mon, 01/04/2016 - 05:33 1
by Simon Johnson (...
Mon, 01/04/2016 - 07:51
Normal topic How Profile a program that have avx instructions
by Innocenzo M.
Fri, 12/18/2015 - 07:40 6
by iliyapolak
Thu, 12/24/2015 - 02:29
Normal topic AVX Base and Turbo Frequencies on non E5 CPUs
by Andrew L.
Mon, 10/19/2015 - 16:22 5
by iliyapolak
Fri, 12/18/2015 - 12:33
Hot topic Massive speedup of integer SSE2 code using AVX1(!)
by Nikos D.
Sun, 09/06/2015 - 22:32 28
by iliyapolak
Wed, 12/16/2015 - 12:58
Normal topic How long does a 6700K take to multiply two integers?
by Nosh N.
Fri, 11/06/2015 - 10:13 3
by iliyapolak
Tue, 12/15/2015 - 09:18
Normal topic How to avoid unsupported instructions?
by Stephan D.
Tue, 11/03/2015 - 07:23 2
by areid
Tue, 11/03/2015 - 14:17
Normal topic AVX512 for mobile?
by Travis D.
Wed, 09/16/2015 - 13:03 7
by McCalpin, John
Wed, 10/21/2015 - 16:06
Normal topic Possible bug in SDE - jump with 16-bit operand size
by Michael R.
Tue, 10/20/2015 - 14:00 3
by Mark Charney (Intel)
Wed, 10/21/2015 - 04:58
Normal topic IRET Pseudo-code Bug
by Philip S.
Thu, 07/23/2015 - 07:46 7
by Mark Charney (Intel)
Thu, 10/15/2015 - 11:56
Normal topic Processor models supporting the SHA extensions?
by areid
Sat, 10/10/2015 - 01:23 2
by areid
Sat, 10/10/2015 - 13:46
Normal topic SSE and multiplication
by Frédéric D.
Mon, 10/05/2015 - 08:47 4
by jimdempseyatthecove
Sat, 10/10/2015 - 06:07
Normal topic SDE Message: "No MPX support"
by Markus M.
Mon, 10/05/2015 - 06:11 6
by Markus M.
Mon, 10/05/2015 - 14:45
Normal topic Switching to protected mode clarification
by Nathan P.
Sat, 08/01/2015 - 06:04 4
by Nathan P.
Thu, 10/01/2015 - 05:09
Hot topic Q on memory comparison optimization (Page: 1, 2)
by Ravi K.
Fri, 04/24/2015 - 12:34 51
by andysem
Thu, 10/01/2015 - 03:29
Normal topic IA-32e 64-bit and compatibility mode
by Ravi K.
Tue, 09/15/2015 - 05:12 3
by Ravi K.
Wed, 09/30/2015 - 12:26
Normal topic SDE debugtrace output incomplete
by Michael R.
Thu, 09/24/2015 - 14:14 1
by Mark Charney (Intel)
Thu, 09/24/2015 - 14:24
Normal topic Intel® X86 Encoder Decoder (Intel® XED) - new release site
by Mark Charney (Intel)
Thu, 09/10/2015 - 11:27 0
by Mark Charney (Intel)
Thu, 09/10/2015 - 11:27
Normal topic What is behavior of LD + OP instruction with register source and EVEX.b = 1?
by Michael R.
Thu, 09/10/2015 - 00:44 0
by Michael R.
Thu, 09/10/2015 - 00:44
Normal topic Behavior of some convert instructions with W=1 in non-64-bit mode
by Michael R.
Tue, 09/01/2015 - 17:33 1
by Mark Charney (Intel)
Wed, 09/02/2015 - 04:23
Normal topic BMI support in Skylake
by bronxzv
Tue, 08/18/2015 - 01:41 11
by jimdempseyatthecove
Fri, 08/28/2015 - 08:15
Normal topic No explanation of comparison codes for integer vector compare instructions
by Michael R.
Wed, 07/29/2015 - 14:42 3
by jimdempseyatthecove
Wed, 08/05/2015 - 04:19
Normal topic New extension needed for Maps and Sets
by Mirza H.
Thu, 07/23/2015 - 01:10 4
by jimdempseyatthecove
Thu, 07/30/2015 - 11:41
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Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.