Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic SSE and multiplication
by Frédéric D.
Mon, 10/05/2015 - 08:47 4
by jimdempseyatthecove
Sat, 10/10/2015 - 06:07
Normal topic SDE Message: "No MPX support"
by Markus M.
Mon, 10/05/2015 - 06:11 6
by Markus M.
Mon, 10/05/2015 - 14:45
Normal topic Switching to protected mode clarification
by Nathan P.
Sat, 08/01/2015 - 06:04 4
by Nathan P.
Thu, 10/01/2015 - 05:09
Hot topic Q on memory comparison optimization (Page: 1, 2)
by Ravi K.
Fri, 04/24/2015 - 12:34 51
by andysem
Thu, 10/01/2015 - 03:29
Normal topic IA-32e 64-bit and compatibility mode
by Ravi K.
Tue, 09/15/2015 - 05:12 3
by Ravi K.
Wed, 09/30/2015 - 12:26
Normal topic SDE debugtrace output incomplete
by Michael R.
Thu, 09/24/2015 - 14:14 1
by Mark Charney (Intel)
Thu, 09/24/2015 - 14:24
Normal topic Intel® X86 Encoder Decoder (Intel® XED) - new release site
by Mark Charney (Intel)
Thu, 09/10/2015 - 11:27 0
by Mark Charney (Intel)
Thu, 09/10/2015 - 11:27
Normal topic What is behavior of LD + OP instruction with register source and EVEX.b = 1?
by Michael R.
Thu, 09/10/2015 - 00:44 0
by Michael R.
Thu, 09/10/2015 - 00:44
Normal topic Behavior of some convert instructions with W=1 in non-64-bit mode
by Michael R.
Tue, 09/01/2015 - 17:33 1
by Mark Charney (Intel)
Wed, 09/02/2015 - 04:23
Normal topic BMI support in Skylake
by bronxzv
Tue, 08/18/2015 - 01:41 11
by jimdempseyatthecove
Fri, 08/28/2015 - 08:15
Normal topic No explanation of comparison codes for integer vector compare instructions
by Michael R.
Wed, 07/29/2015 - 14:42 3
by jimdempseyatthecove
Wed, 08/05/2015 - 04:19
Normal topic New extension needed for Maps and Sets
by Mirza H.
Thu, 07/23/2015 - 01:10 4
by jimdempseyatthecove
Thu, 07/30/2015 - 11:41
Normal topic What is syntax for broadcast decorator?
by Michael R.
Sun, 07/26/2015 - 17:51 3
by Alexander F. (Intel)
Thu, 07/30/2015 - 10:49
Normal topic Wrong memory size for VGATHERQPS (?)
by Michael R.
Wed, 07/29/2015 - 13:52 1
by Mark Charney (Intel)
Wed, 07/29/2015 - 14:47
Normal topic Encodings for instructions with {sae} are unclear in the doc
by Michael R.
Wed, 07/22/2015 - 12:23 4
by Mark Charney (Intel)
Wed, 07/22/2015 - 14:05
Normal topic PCI Legacy Mode - Why does it use subtractive decoding?
by Robert S.
Fri, 07/10/2015 - 17:41 1
by Robert S.
Tue, 07/14/2015 - 06:15
Normal topic Dynamic Shift
by Christian M.
Thu, 06/25/2015 - 03:59 6
by Christian M.
Tue, 07/14/2015 - 04:45
Normal topic Processor Trace decoding support library for Atom
by Daniel L.
Mon, 07/06/2015 - 23:26 0
by Daniel L.
Mon, 07/06/2015 - 23:26
Normal topic Ooops - wrong instruction description in volume 2 of the SDM
by McCalpin, John
Thu, 07/02/2015 - 11:39 1
by Mark Charney (Intel)
Thu, 07/02/2015 - 12:20
Normal topic MPX instructions not in the Appendix A opcode map
by Bea T.
Wed, 07/01/2015 - 14:28 0
by Bea T.
Wed, 07/01/2015 - 14:28
Normal topic Guaranteed atomic operation clarification
by Nathan P.
Mon, 06/29/2015 - 20:52 2
by Nathan P.
Tue, 06/30/2015 - 17:26
Normal topic small typo in Intel® 64 and IA-32 Architectures Software Developer’s Manual
by Bea T.
Tue, 06/30/2015 - 02:31 1
by Mark Charney (Intel)
Tue, 06/30/2015 - 05:22
Normal topic the issue about APIC drop msix interrupt
by wei j.
Sun, 06/28/2015 - 18:27 0
by wei j.
Sun, 06/28/2015 - 18:27
Normal topic Capacity abort when using RTM provided by haswell
by zhaoguo w.
Sat, 06/15/2013 - 01:55 2
by McCalpin, John
Fri, 06/19/2015 - 08:12
Normal topic Why is my AVX slower than SSE?
by Shaquille W.
Tue, 06/02/2015 - 09:18 3
by Tim P.
Wed, 06/10/2015 - 12:59
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Hot topic with new posts
Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.