Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

Topic / Topic starter Post date Replies Last Postsort descending
Normal topic We need standardization of the x86 instruction set
by Agner
Sat, 12/05/2009 - 09:35 10
by Igor Levicki
Sat, 12/05/2009 - 09:35
Normal topic ow to calculate latency and throughput of instruction?
by maa1
Thu, 12/17/2009 - 10:32 2
by maa1
Thu, 12/17/2009 - 10:32
Normal topic question on avx instruction encoding
by tthsqe
Fri, 01/01/2010 - 02:19 9
by mariaosawa
Fri, 01/01/2010 - 02:19
Normal topic Debugging SSE/SSE2 ?
by gol
Thu, 12/24/2009 - 03:26 10
by gol
Wed, 01/06/2010 - 04:54
Normal topic mul instruction latency
by tthsqe
Sat, 01/09/2010 - 22:52 3
by Max Locktyukhin...
Sat, 01/09/2010 - 22:52
Normal topic TSC Problem
by faball
Fri, 11/27/2009 - 02:52 0
by faball
Mon, 01/11/2010 - 09:36
Normal topic Could intel somehow initiate migration/cleanup for x86 instruction set?
by htuh
Thu, 11/12/2009 - 16:13 0
by htuh
Tue, 01/12/2010 - 10:45
Normal topic Performance boost is not as expected using SSE intrinsics
by joggingsonggmail.com
Mon, 01/18/2010 - 23:07 6
by bronxzv
Mon, 01/18/2010 - 23:07
Normal topic Core2 Quad (S)SSE 3/4
by ocirne94
Sat, 01/23/2010 - 06:52 4
by Tim Prince
Sat, 01/23/2010 - 06:52
Normal topic SSE4
by hjazz
Mon, 01/25/2010 - 23:28 2
by hjazz
Tue, 01/26/2010 - 17:30
Normal topic uops? IA32/Intel64 vs. micro-ops?
by arrazem
Wed, 01/27/2010 - 20:31 4
by Max Locktyukhin...
Wed, 01/27/2010 - 20:31
Normal topic Can MPI based application be run on SDE ?
by jnzhoun
Thu, 01/28/2010 - 23:44 3
by jnzhoun
Thu, 01/28/2010 - 23:44
Normal topic about the reserved field in cpuid
by hurricanezhb
Fri, 01/29/2010 - 13:08 2
by Max Locktyukhin...
Fri, 01/29/2010 - 13:08
Normal topic Core 2 MSR register documentation
by elmo234
Tue, 06/17/2008 - 10:24 8
by yuhong2
Mon, 02/01/2010 - 20:48
Normal topic Intel(R) SDE 2.94 release announcement
by Mark Charney (Intel)
Thu, 12/31/2009 - 13:07 6
by twilkens
Tue, 02/02/2010 - 08:19
Normal topic Undocumented MSRs
by isakovsl
Wed, 02/03/2010 - 03:55 0
by isakovsl
Wed, 02/03/2010 - 03:55
Normal topic Unresolved SSE instructions
by changbo
Fri, 02/12/2010 - 06:19 2
by Brijender Bhart...
Fri, 02/19/2010 - 08:06
Normal topic Weeks of optimizations and still can't beat the intel compiler
by mr_nuke
Fri, 02/19/2010 - 08:34 9
by tthsqe
Fri, 02/19/2010 - 08:38
Normal topic Where to Find Intel MMX SIMD Examples
by iekpo
Thu, 02/11/2010 - 13:37 4
by iekpo
Fri, 02/19/2010 - 11:46
Normal topic does pentium E5300 have 2 physical cores ?
by ilbeydinler
Thu, 02/25/2010 - 13:13 2
by ilbeydinler
Thu, 02/25/2010 - 14:00
Normal topic Update Bios lennovo t400
by hoapq
Thu, 02/25/2010 - 23:29 1
by Thomas Willhalm...
Thu, 02/25/2010 - 23:29
Normal topic Xed / Objdump errors in disassembly of Intel compiled executables...
by twilkens
Fri, 02/26/2010 - 16:56 2
by twilkens
Fri, 02/26/2010 - 16:56
Normal topic About the x64 stack Alignment
by xfcyhuang
Sun, 02/28/2010 - 10:23 5
by neerajsi_msft
Sun, 02/28/2010 - 15:06
Normal topic AVX/YMM registers and Win64 ABI
by yuhong2
Thu, 03/04/2010 - 17:04 4
by neerajsi_msft
Fri, 03/05/2010 - 09:01
Normal topic Intel I7 - 860 help.
by chadr
Mon, 03/08/2010 - 08:33 2
by Tim Prince
Mon, 03/08/2010 - 08:33
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For more complete information about compiler optimizations, see our Optimization Notice.