Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX, a security technology designed for developers wanting to protect select application code and data from disclosure or modification
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic startersort descending Post date Replies Last Post
Normal topic Detecting AVX
by smidla
Wed, 08/24/2011 - 16:32 5
by Pourya Shirazian
Wed, 10/26/2011 - 10:58
Normal topic Detecting Core
by knujohn4
Tue, 05/11/2010 - 02:15 2
by knujohn4
Tue, 05/11/2010 - 02:15
Normal topic Detecting Nehalem CPU
by dark_shikari
Fri, 10/10/2008 - 15:24 5
by Shih Kuo (Intel)
Fri, 10/17/2008 - 18:26
Normal topic determining L1 and L2 cache state
by maamold
Tue, 08/25/2009 - 10:00 0
by maamold
Tue, 08/25/2009 - 10:00
Normal topic Diagnostic testing of CPU and Support Device Architectures
by daryl_langley_4
Mon, 12/01/2008 - 17:06 1
by Thai Le (Intel)
Tue, 12/09/2008 - 13:51
Normal topic Difference between L2 cache misses and Bus_Trans_Mem
by gokussj9
Mon, 09/27/2010 - 15:13 1
by neni
Mon, 09/27/2010 - 15:13
Normal topic Difference using SSE on Intel and AMD processors (?)
by (name withheld)
Sat, 09/16/2006 - 21:11 4
by jimdempseyatthecove
Mon, 09/25/2006 - 14:11
Normal topic Different ways to turn an AoS into an SoA
by Diego Caballero
Sat, 02/08/2014 - 03:13 6
by Diego Caballero
Fri, 02/21/2014 - 02:09
Normal topic Disable SSE* instructions
by Hsunwei H.
Mon, 06/16/2014 - 21:56 6
by John McCalpin
Wed, 06/18/2014 - 07:02
Hot topic Disabling AVX
by emmanuel.attia
Wed, 03/26/2014 - 10:36 17
by iliyapolak
Fri, 03/28/2014 - 03:21
Normal topic Display problem
by jayarajnayak
Fri, 02/27/2009 - 23:14 2
by coolman010
Fri, 02/27/2009 - 23:14
Hot topic division sse2 intrinsic
by Smart Lubobya
Thu, 05/27/2010 - 06:50 16
by Thomas Willhalm...
Fri, 01/07/2011 - 05:33
Normal topic Do Non-Temporal Loads Prefetch?
by Nicholas B.
Wed, 10/21/2015 - 02:36 6
by Nicholas B.
Wed, 10/21/2015 - 16:03
Normal topic Do the Intel 11.1 compilers support AVX?
by twilkens
Wed, 06/24/2009 - 17:08 5
by twilkens
Wed, 06/24/2009 - 17:08
Normal topic do _mm256_load_ps slower than _mm_load_ps?
by zhang h.
Mon, 09/09/2013 - 20:40 14
by Sergey Kostrov
Fri, 11/01/2013 - 14:10
Normal topic Documentation bug for DIV/IDIV
by sirrida
Sat, 07/19/2014 - 10:23 0
by sirrida
Sat, 07/19/2014 - 10:23
Normal topic Documentation of SSE versions
by Christian M.
Thu, 02/21/2013 - 02:10 7
by Christian M.
Sat, 03/09/2013 - 03:57
Normal topic Documentation suggestion
by jimdempseyatthecove
Fri, 02/06/2009 - 07:15 1
by Shih Kuo (Intel)
Fri, 02/06/2009 - 07:15
Normal topic Does Intel Software Development Emulator support SSE3 instruction set?
by Sergey Kostrov
Tue, 01/17/2012 - 20:48 5
by Mark Charney (Intel)
Wed, 01/18/2012 - 18:24
Normal topic Does LBR_SELECT apply to BTF?
by tarmeneldur
Fri, 04/02/2010 - 11:20 2
by tarmeneldur
Fri, 04/02/2010 - 11:24
Normal topic does pentium E5300 have 2 physical cores ?
by ilbeydinler
Thu, 02/25/2010 - 13:13 2
by ilbeydinler
Thu, 02/25/2010 - 14:00
Normal topic Does the cache prefetcher will abort the rtm transaction?
by zhaoguo w.
Sat, 06/22/2013 - 06:56 5
by John McCalpin
Mon, 06/24/2013 - 15:46
Normal topic does this exception/interrupt handler run?
by logicman112
Mon, 09/06/2010 - 23:44 0
by logicman112
Mon, 09/06/2010 - 23:44
Normal topic Does VPMASKMOV require an aligned address?
by Nathan K.
Tue, 12/09/2014 - 18:14 9
by John McCalpin
Sat, 12/13/2014 - 11:48
Normal topic Dot Products and overhead of Address increments....
by k_sarnath
Wed, 06/02/2010 - 04:29 10
by Tim P.
Fri, 06/04/2010 - 05:56
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.