Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
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Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic what micro-operations (uops) instruction decoded?
by zhangxiuxia
Wed, 05/18/2011 - 07:33 3
by iliyapolak
Mon, 09/23/2013 - 07:24
Hot topic AVX-512 expectations
by c0d1f1ed
Fri, 07/26/2013 - 23:24 29
by iliyapolak
Sun, 09/22/2013 - 23:14
Normal topic Unable to ative the SSE nstruction set byadding compile flag “march=native” in gcc
by Chenjie Y.
Sat, 08/31/2013 - 03:25 7
by Sergey Kostrov
Sun, 09/22/2013 - 22:34
Normal topic Is Haswell's new transactional memory 'TSX' actually slower than locking?
by Elmar
Thu, 08/29/2013 - 09:28 6
by jimdempseyatthecove
Fri, 09/06/2013 - 06:01
Normal topic Why weren't PINSR* instructions extended to 256-bits in AVX2
by perfwise
Tue, 08/27/2013 - 20:24 3
by perfwise
Fri, 08/30/2013 - 06:06
Normal topic Question/Advice on PERMD and PERMPS..
by perfwise
Tue, 08/27/2013 - 06:19 0
by perfwise
Tue, 08/27/2013 - 06:19
Normal topic monitor/mwait performance differs in different memory addresses
by Hamid b.
Thu, 07/11/2013 - 08:40 7
by iliyapolak
Thu, 08/01/2013 - 10:33
Normal topic Typing errors in xmm_func.h header file for _mm_prefetch intrinsic function
by Sergey Kostrov
Tue, 07/30/2013 - 17:51 1
by Sergey Kostrov
Tue, 07/30/2013 - 17:53
Normal topic intrinsic for CPUID like informations
by bp
Fri, 07/19/2013 - 21:09 12
by Sergey Kostrov
Mon, 07/29/2013 - 23:08
Hot topic Haswell GFLOPS (Page: 1, 2)
by caosun
Wed, 06/26/2013 - 02:42 71
by perfwise
Mon, 07/29/2013 - 05:46
Normal topic SSE2 vectorized code seems to run slower than non-vectorized code
by (name withheld)
Thu, 07/11/2013 - 08:05 12
by iliyapolak
Sun, 07/28/2013 - 02:40
Hot topic Question about example on Optimization manual---AVX mask move to avoid branch penalty
by Deyang Gu
Tue, 06/25/2013 - 11:07 31
by jimdempseyatthecove
Sat, 07/27/2013 - 06:53
Normal topic Detailed idata.txt
by Antonio O.
Thu, 07/25/2013 - 14:15 2
by Antonio O.
Fri, 07/26/2013 - 02:19
Normal topic Instruction set extensions programming reference, revision 15
by Mark Charney (Intel)
Tue, 07/23/2013 - 10:45 0
by Mark Charney (Intel)
Tue, 07/23/2013 - 10:45
Normal topic Intel® Software Development Emulator, Release 6.1
by Mark Charney (Intel)
Tue, 07/23/2013 - 10:09 0
by Mark Charney (Intel)
Tue, 07/23/2013 - 10:09
Hot topic SSE4 Register-Handling
by adrian s.
Wed, 07/10/2013 - 07:58 21
by Sergey Kostrov
Thu, 07/18/2013 - 18:38
Normal topic Almost-unit-stride stores
by Fabio L.
Mon, 07/01/2013 - 09:21 3
by jimdempseyatthecove
Thu, 07/18/2013 - 07:40
Normal topic simple question about avx instructions.
by Roberto O.
Mon, 07/15/2013 - 06:42 1
by Tim P.
Mon, 07/15/2013 - 08:42
Hot topic To use FPU
by GHui
Fri, 06/28/2013 - 02:13 23
by GHui
Thu, 07/11/2013 - 09:27
Hot topic IPP causes invalid opcode exception at h9_ippsFFTGetSize_C_32fc
by Beni F.
Tue, 06/25/2013 - 06:17 29
by Beni F.
Thu, 06/27/2013 - 10:02
Normal topic Why the restricted transaction has conflict abort even run a single thread?
by zhaoguo w.
Mon, 06/24/2013 - 05:45 12
by Roman Dementiev...
Tue, 06/25/2013 - 07:17
Normal topic Capacity abort when using RTM provided by haswell
by zhaoguo w.
Sat, 06/15/2013 - 01:59 4
by Roman Dementiev...
Tue, 06/25/2013 - 03:48
Normal topic Looking for smartest way to insert a DWORD into AVX register
by Elmar
Thu, 06/20/2013 - 05:39 8
by andysem
Tue, 06/25/2013 - 00:30
Normal topic Does the cache prefetcher will abort the rtm transaction?
by zhaoguo w.
Sat, 06/22/2013 - 06:56 5
by John McCalpin
Mon, 06/24/2013 - 15:46
Normal topic Function Vectorization
by Vahid N.
Fri, 06/14/2013 - 13:51 10
by Sergey Kostrov
Tue, 06/18/2013 - 16:23
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.