Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Postsort descending
Normal topic Blocks in mix output truncated at 70 instructions..
by perfwise
Sat, 03/13/2010 - 21:18 5
by Mark Charney (Intel)
Sat, 03/13/2010 - 21:18
Normal topic help on xed in avx package
by jnzhoun
Tue, 03/23/2010 - 21:20 3
by smith001
Tue, 03/23/2010 - 21:20
Normal topic x87 and out-of-order execution
by k_sarnath
Wed, 03/31/2010 - 22:33 2
by k_sarnath
Wed, 03/31/2010 - 22:33
Normal topic Does LBR_SELECT apply to BTF?
by tarmeneldur
Fri, 04/02/2010 - 11:20 2
by tarmeneldur
Fri, 04/02/2010 - 11:24
Normal topic LBR_SELECT in Nehalem - strange behaviour
by tarmeneldur
Wed, 04/07/2010 - 11:47 0
by tarmeneldur
Wed, 04/07/2010 - 11:50
Normal topic Cycle counts of the new Westmere instructions
by Cryptographer
Tue, 04/13/2010 - 00:10 2
by neni
Tue, 04/13/2010 - 00:10
Normal topic Need You Help For My Intel P C
by jackdalson
Wed, 04/21/2010 - 06:21 1
by Thomas Willhalm...
Wed, 04/21/2010 - 06:21
Normal topic Performance of SHA-3 hash functions on Intel processors (Core 2 platform vs Itanium)
by gligoroski
Wed, 04/21/2010 - 07:18 1
by gligoroski
Wed, 04/21/2010 - 07:20
Normal topic SDE disassembly and MS windows disassembly discrepencies
by perfwise
Fri, 04/23/2010 - 14:34 5
by bronxzv
Fri, 04/23/2010 - 14:34
Normal topic SDE execution Error (April, 29, 2010)
by inteleverywhere
Wed, 04/28/2010 - 22:46 8
by bronxzv
Fri, 04/30/2010 - 09:19
Normal topic Processor Cycle and Execution Time of Instruction
by Mathew, Eldho P
Sun, 05/02/2010 - 22:59 2
by Roman Dementiev...
Sun, 05/02/2010 - 23:02
Normal topic Cache Optimization
by xift
Thu, 05/06/2010 - 03:48 8
by Thomas Willhalm...
Thu, 05/06/2010 - 03:48
Normal topic __m128 array becomes unaligned with IC optimization
by Taylor IoT Kidd
Fri, 05/07/2010 - 15:43 5
by Igor Levicki
Fri, 05/07/2010 - 15:43
Normal topic How to convert three 8-bit 1-channel images to a 24-bit three channels image using SSE
by softwarebee
Mon, 05/10/2010 - 05:26 7
by softwarebee
Mon, 05/10/2010 - 05:27
Normal topic Detecting Core
by knujohn4
Tue, 05/11/2010 - 02:15 2
by knujohn4
Tue, 05/11/2010 - 02:15
Normal topic From Gulftown to Sandy Bridge
by Cryptographer
Mon, 05/17/2010 - 02:45 2
by Cryptographer
Mon, 05/17/2010 - 02:45
Normal topic how do i use if-else statement in sse2 intrinsics
by Smart Lubobya
Wed, 05/26/2010 - 03:54 1
by bronxzv
Wed, 05/26/2010 - 03:57
Normal topic how to display output in sse intrinsic codes
by Smart Lubobya
Mon, 05/31/2010 - 02:52 4
by bronxzv
Mon, 05/31/2010 - 02:56
Normal topic Are FMA instructions supported with the intel compiler?
by rlaouenan
Tue, 06/01/2010 - 04:17 0
by rlaouenan
Tue, 06/01/2010 - 04:17
Normal topic Larrabee docs
by Wolfgang Bauer
Wed, 06/02/2010 - 01:56 3
by knujohn4
Wed, 06/02/2010 - 01:56
Normal topic P-State invariant TSC on Nehalem platforms with multi-packages
by pisymbol
Wed, 06/02/2010 - 09:04 3
by Igor Levicki
Wed, 06/02/2010 - 09:22
Normal topic Dot Products and overhead of Address increments....
by k_sarnath
Wed, 06/02/2010 - 04:29 10
by Tim P.
Fri, 06/04/2010 - 05:56
Normal topic operand size override prefix(66H)
by logicman112
Mon, 06/07/2010 - 20:38 0
by logicman112
Mon, 06/07/2010 - 20:38
Normal topic How do you do for access the instructions of the processor.
by wendel-sm
Thu, 06/10/2010 - 11:58 1
by Aubrey W.
Thu, 06/10/2010 - 11:58
Normal topic Intel documentation seems to have wrong or ambiguous information!
by logicman112
Sun, 06/13/2010 - 21:24 1
by mecej4
Sun, 06/13/2010 - 21:24
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For more complete information about compiler optimizations, see our Optimization Notice.