Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Repliessort descending Last Post
Sticky topic Sticky: Intel® Software Development Emulator release 7.30
by Mark Charney (Intel)
Mon, 09/21/2015 - 05:23 3
by Sergio J. C.
Wed, 12/16/2015 - 12:26
Sticky topic Sticky: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
by Roman Dementiev...
Fri, 06/07/2013 - 06:46 6
by D. Hugh R.
Sat, 05/21/2016 - 09:28
Sticky topic Sticky: Links to instruction documentation
by Thomas Willhalm...
Fri, 12/31/2010 - 07:07 30
by John McCalpin
Wed, 08/10/2016 - 11:51
Normal topic quad core q9550 question
by threetwo
Wed, 07/08/2009 - 09:47 0
by threetwo
Wed, 07/08/2009 - 09:47
Normal topic LBR_SELECT in Nehalem - strange behaviour
by tarmeneldur
Wed, 04/07/2010 - 11:47 0
by tarmeneldur
Wed, 04/07/2010 - 11:50
Normal topic How does address be mapped onto a memory bank
by zhangyihere
Tue, 12/01/2009 - 02:04 0
by zhangyihere
Tue, 12/01/2009 - 07:30
Normal topic Documentation bug for DIV/IDIV
by sirrida
Sat, 07/19/2014 - 10:23 0
by sirrida
Sat, 07/19/2014 - 10:23
Normal topic ICPC 13.0.2 generates scalar load instead of packed load
by Paul S.
Wed, 01/15/2014 - 01:45 0
by Paul S.
Wed, 01/15/2014 - 01:45
Normal topic the issue about APIC drop msix interrupt
by wei j.
Sun, 06/28/2015 - 18:27 0
by wei j.
Sun, 06/28/2015 - 18:27
Normal topic Compiler optimization for SSE4.2 and AVX
by Tim P.
Wed, 05/20/2009 - 10:24 0
by Tim P.
Wed, 05/20/2009 - 10:24
Normal topic GCC + static libmpx
by Nick A.
Thu, 03/24/2016 - 19:19 0
by Nick A.
Thu, 03/24/2016 - 19:19
Normal topic Instruction decoder
by rediclo
Tue, 02/10/2009 - 09:06 0
by rediclo
Tue, 02/10/2009 - 09:06
Normal topic Low rate on sse2 code
by maa1
Mon, 11/23/2009 - 11:39 0
by maa1
Mon, 11/23/2009 - 11:39
Normal topic Instruction set extensions programming reference, revision 15
by Mark Charney (Intel)
Tue, 07/23/2013 - 10:45 0
by Mark Charney (Intel)
Tue, 07/23/2013 - 10:45
Normal topic Forums will be read-only 09/24 10PM PST to 09/25 12PM PST
by Intel Software ...
Mon, 09/22/2008 - 11:46 0
by Intel Software ...
Mon, 09/22/2008 - 11:46
Normal topic [smp] Initialization
by medinad
Mon, 09/21/2009 - 08:11 0
by medinad
Mon, 09/21/2009 - 08:11
Normal topic RDRAND and Ivy Bridge Celerons
by D. Hugh R.
Sat, 05/21/2016 - 08:43 0
by D. Hugh R.
Sat, 05/21/2016 - 08:43
Normal topic pentium cache
by luca83
Thu, 03/26/2009 - 01:01 0
by luca83
Thu, 03/26/2009 - 01:01
Normal topic Intel(R) Software development emulator 4.29 released - Haswell New Instructions
by Mark Charney (Intel)
Fri, 07/01/2011 - 12:24 0
by Mark Charney (Intel)
Fri, 12/16/2011 - 07:29
Normal topic C-State Configuration
by rdmsr64
Thu, 05/12/2011 - 04:49 0
by rdmsr64
Thu, 05/12/2011 - 04:49
Normal topic does this exception/interrupt handler run?
by logicman112
Mon, 09/06/2010 - 23:44 0
by logicman112
Mon, 09/06/2010 - 23:44
Normal topic Intel Systems Programmers Manual query
by dkandula
Tue, 05/24/2011 - 15:01 0
by dkandula
Tue, 05/24/2011 - 15:01
Normal topic Intel® X86 Encoder Decoder (Intel® XED) - new release site
by Mark Charney (Intel)
Thu, 09/10/2015 - 11:27 0
by Mark Charney (Intel)
Thu, 09/10/2015 - 11:27
Normal topic MPX instructions not in the Appendix A opcode map
by Bea T.
Wed, 07/01/2015 - 14:28 0
by Bea T.
Wed, 07/01/2015 - 14:28
Normal topic Intel C++ : _mm256_set1_ps suboptimal ?
by bronxzv
Sun, 08/09/2009 - 15:45 0
by bronxzv
Sun, 08/09/2009 - 15:45
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.