Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX, a security technology designed for developers wanting to protect select application code and data from disclosure or modification
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Post
Sticky topic Sticky: Links to instruction documentation
by Thomas Willhalm...
Fri, 12/31/2010 - 07:07 26
by Sergio J. C.
Wed, 12/16/2015 - 11:40
Sticky topic Sticky: Intel® Software Development Emulator release 7.30
by Mark Charney (Intel)
Mon, 09/21/2015 - 05:23 3
by Sergio J. C.
Wed, 12/16/2015 - 12:26
Sticky topic Sticky: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
by Roman Dementiev...
Fri, 06/07/2013 - 06:46 5
by Sergio J. C.
Wed, 12/16/2015 - 11:36
Normal topic AVX performance question
by xman.hawkeye
Thu, 02/28/2013 - 15:25 7
by iliyapolak
Tue, 03/12/2013 - 22:22
Normal topic seems to be a mistake, regarding manuals, 64 bit push/pop operation
by logicman112
Fri, 08/13/2010 - 21:31 1
by Shih Kuo (Intel)
Fri, 08/13/2010 - 21:31
Normal topic Invariant TSC support
by Bryan Hickman (...
Wed, 12/21/2011 - 10:03 10
by John McCalpin
Wed, 02/19/2014 - 06:53
Normal topic SSE3 critique
by Deleted User
Fri, 08/19/2005 - 08:35 3
by Igor Levicki
Tue, 05/27/2008 - 09:59
Normal topic Need help: Why my avx code is slower than SSE code?
by Chen S.
Sun, 06/08/2014 - 04:38 8
by emmanuel.attia
Mon, 06/16/2014 - 09:45
Normal topic Error code of einit
by gu j.
Mon, 01/04/2016 - 05:33 1
by Simon Johnson (...
Mon, 01/04/2016 - 07:51
Normal topic inc/dec instruction vs macrofusion
by rivet_amber
Sun, 01/20/2013 - 08:00 3
by Tim P.
Mon, 01/21/2013 - 05:48
Normal topic Instruction set latency
by sebitab
Thu, 04/16/2009 - 14:51 4
by Tal Uliel (Intel)
Thu, 04/16/2009 - 14:51
Normal topic AVX Performance Measure
by inteleverywhere
Thu, 06/24/2010 - 05:48 1
by Tim P.
Thu, 06/24/2010 - 05:48
Normal topic Intel MIC(Many Integrated Core)
by zhangxiuxia
Tue, 07/12/2011 - 05:19 10
by Tim P.
Wed, 07/20/2011 - 05:03
Normal topic MOVNTI and alignment for real mode
by Kostik B.
Tue, 12/03/2013 - 08:00 2
by iliyapolak
Sat, 12/07/2013 - 11:14
Normal topic Encodings for instructions with {sae} are unclear in the doc
by Michael R.
Wed, 07/22/2015 - 12:23 4
by Mark Charney (Intel)
Wed, 07/22/2015 - 14:05
Normal topic constants in SIMD inline assembly
by Smart Lubobya
Sun, 02/20/2011 - 03:05 1
by Max Locktyukhin...
Sun, 02/20/2011 - 03:05
Normal topic Got BSOD with KeSaveExtendedProcessorState
by David Chou (Intel)
Mon, 08/27/2012 - 18:16 4
by Igor Levicki
Tue, 09/25/2012 - 02:33
Normal topic About 256 bit registers
by gabest
Fri, 12/19/2008 - 21:31 5
by Igor Levicki
Thu, 01/01/2009 - 01:07
Normal topic Intel SDE and Windows 10 Preview
by John D.
Sat, 05/02/2015 - 07:12 2
by MICHAEL G.
Sun, 05/03/2015 - 02:13
Normal topic LBR_SELECT in Nehalem - strange behaviour
by tarmeneldur
Wed, 04/07/2010 - 11:47 0
by tarmeneldur
Wed, 04/07/2010 - 11:50
Hot topic Converging AVX and LRBni (Page: 1, 2)
by c0d1f1ed
Tue, 05/10/2011 - 23:27 62
by c0d1f1ed
Fri, 07/01/2011 - 03:59
Normal topic Why only CS, IP and EFLAGS are saved while interrupt??
by cgopi24
Fri, 09/25/2009 - 09:29 1
by Shih Kuo (Intel)
Fri, 10/16/2009 - 01:34
Normal topic Why the restricted transaction has conflict abort even run a single thread?
by zhaoguo w.
Mon, 06/24/2013 - 05:45 12
by Roman Dementiev...
Tue, 06/25/2013 - 07:17
Normal topic MMX intrinsics performed bad
by Smart Lubobya
Tue, 10/19/2010 - 10:27 1
by Thomas Willhalm...
Tue, 10/19/2010 - 10:27
Normal topic Wierd instruction: extractps
by zhangxiuxia
Fri, 04/20/2012 - 04:33 3
by bronxzv
Sun, 05/27/2012 - 01:53
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.