Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX, a security technology designed for developers wanting to protect select application code and data from disclosure or modification
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Post
Normal topic About 256 bit registers
by gabest
Fri, 12/19/2008 - 21:31 5
by Igor Levicki
Thu, 01/01/2009 - 01:07
Normal topic AVX Performance Measure
by inteleverywhere
Thu, 06/24/2010 - 05:48 1
by Tim P.
Thu, 06/24/2010 - 05:48
Normal topic Intel MIC(Many Integrated Core)
by zhangxiuxia
Tue, 07/12/2011 - 05:19 10
by Tim P.
Wed, 07/20/2011 - 05:03
Normal topic Why the restricted transaction has conflict abort even run a single thread?
by zhaoguo w.
Mon, 06/24/2013 - 05:45 12
by Roman Dementiev...
Tue, 06/25/2013 - 07:17
Normal topic Why "subq" as allocate by ICC-v10.0 but not as prologue, but ICC-v11.0 uses "pushq" as prologue?
by srimks
Wed, 01/21/2009 - 01:10 3
by Sergey Maslov (...
Mon, 11/02/2009 - 22:18
Normal topic MOVD: Zero-extension of general purpose register as destination
by Adam Warner
Mon, 07/12/2010 - 23:41 2
by Adam Warner
Mon, 07/12/2010 - 23:41
Normal topic SSE 3.0, SSE 4.2 in visual studio 2010 ultimate
by arrahul
Thu, 07/28/2011 - 12:53 12
by sukruth-v (Intel)
Wed, 05/08/2013 - 23:13
Hot topic Haswell TLBs undefined in Intel cpu spec
by perfwise
Tue, 07/02/2013 - 14:37 15
by perfwise
Thu, 10/31/2013 - 13:48
Normal topic Out of order execution
by tthsqe
Thu, 10/15/2009 - 23:53 9
by tthsqe
Thu, 10/15/2009 - 23:53
Normal topic Obtain time stamp disable (TSD) flag in user-mode
by freeze2046
Tue, 03/29/2011 - 05:54 1
by Chris Hooper
Tue, 03/29/2011 - 05:54
Normal topic vperm2f128 operands
by Bill P.
Fri, 10/26/2012 - 07:32 1
by Thomas Willhalm...
Fri, 11/23/2012 - 06:53
Normal topic PCIe Root Complex and the PCH
by Robert S.
Fri, 12/19/2014 - 16:36 3
by Robert S.
Tue, 12/23/2014 - 17:40
Normal topic code optimization and vtune
by Zhiyong Z.
Tue, 01/12/2016 - 14:03 8
by iliyapolak
Thu, 01/14/2016 - 09:51
Normal topic P4 stalls for >240 uSec
by stevek999
Fri, 07/11/2008 - 06:28 6
by Igor Levicki
Tue, 08/05/2008 - 05:18
Normal topic Cache Optimization
by xift
Thu, 05/06/2010 - 03:48 8
by Thomas Willhalm...
Thu, 05/06/2010 - 03:48
Normal topic what micro-operations (uops) instruction decoded?
by zhangxiuxia
Wed, 05/18/2011 - 07:33 3
by iliyapolak
Mon, 09/23/2013 - 07:24
Normal topic Prefetch instructions
by bronxzv
Sat, 04/13/2013 - 03:20 5
by iliyapolak
Sat, 04/20/2013 - 23:30
Normal topic Generating Prefetch Instructions in AVX code...
by twilkens
Thu, 07/30/2009 - 10:49 5
by Martyn Corden (...
Tue, 08/04/2009 - 11:40
Normal topic Newbie: SSE with integers
by spertulo
Tue, 11/16/2010 - 01:32 5
by 0xr
Tue, 11/16/2010 - 01:32
Normal topic Cross lane operations, how?
by Igor Levicki
Mon, 05/21/2012 - 05:25 9
by sirrida
Thu, 05/24/2012 - 03:16
Normal topic Documentation bug for DIV/IDIV
by sirrida
Sat, 07/19/2014 - 10:23 0
by sirrida
Sat, 07/19/2014 - 10:23
Normal topic I210 driver delevopment (DOS)
by Jonathan M.
Fri, 08/07/2015 - 05:51 1
by Igor Levicki
Fri, 08/28/2015 - 04:43
Normal topic Missing instruction in SSE: PSLLDQ with _bit_ shift amount?
by geofflangdale
Thu, 02/28/2008 - 15:33 4
by happyIntelCamper
Thu, 02/28/2008 - 15:33
Normal topic question on avx instruction encoding
by tthsqe
Fri, 01/01/2010 - 02:19 9
by mariaosawa
Fri, 01/01/2010 - 02:19
Normal topic sse4.2 instructions
by westmere
Fri, 05/01/2009 - 16:03 7
by Shih Kuo (Intel)
Mon, 11/02/2009 - 09:54
New posts
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Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.