Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Topic / Topic starter Post date Replies Last Post
Normal topic Intel Intrinsic Guide problem
by foxtoxer
Mon, 12/26/2011 - 06:15 7
by Patrick Konsor ...
Mon, 02/13/2012 - 09:59
Normal topic Question about write SIMD code mannually
by Raymond S.
Fri, 04/22/2016 - 00:35 1
by McCalpin, John
Fri, 04/22/2016 - 10:57
Normal topic CPU temperature Pentium 4
by abdekker
Wed, 06/18/2008 - 10:07 1
by Igor Levicki
Thu, 07/10/2008 - 21:01
Normal topic Benefits of SSE/AVX processing when an integrated GPU is missing?
by Toby
Tue, 12/16/2014 - 07:08 5
by Toby
Tue, 12/16/2014 - 09:35
Normal topic Cycle counts of the new Westmere instructions
by Cryptographer
Tue, 04/13/2010 - 00:10 2
by neni
Tue, 04/13/2010 - 00:10
Normal topic Small typo in Software Development Manual Vol.1 (Version 043)
by rivet_amber
Mon, 07/02/2012 - 14:23 0
by rivet_amber
Mon, 07/02/2012 - 14:23
Normal topic Code scales poorly with AVX
by CommanderLake
Wed, 01/11/2017 - 18:32 11
by CommanderLake
Tue, 01/17/2017 - 00:32
Normal topic monitor/mwait disabled by IA32_MISC_ENABLES MSR?
by godofpumpkins
Fri, 02/13/2009 - 19:11 3
by Igor Levicki
Sat, 02/14/2009 - 11:02
Normal topic No explanation of comparison codes for integer vector compare instructions
by Michael R.
Wed, 07/29/2015 - 14:42 3
by jimdempseyatthecove
Wed, 08/05/2015 - 04:19
Normal topic adding a constant to array addition in sse2
by Smart Lubobya
Sun, 07/25/2010 - 07:19 1
by Brijender Bhart...
Tue, 07/27/2010 - 11:13
Normal topic Padding does not help AVX
by Fabio L.
Fri, 01/25/2013 - 01:54 1
by Sergey Kostrov
Fri, 01/25/2013 - 06:10
Normal topic quad core q9550 question
by threetwo
Wed, 07/08/2009 - 09:47 0
by threetwo
Wed, 07/08/2009 - 09:47
Normal topic _byteswap_ulong
by ms2579
Wed, 10/20/2010 - 09:47 1
by Nicolae Popovic...
Wed, 10/20/2010 - 09:47
Normal topic Array of _m128d values as function argument
by n.anastop
Tue, 03/19/2013 - 06:43 8
by iliyapolak
Fri, 03/22/2013 - 05:42
Normal topic TSC Problem
by faball
Fri, 11/27/2009 - 02:52 0
by faball
Mon, 01/11/2010 - 09:36
Hot topic Converging AVX and LRBni (Page: 1, 2)
by c0d1f1ed
Tue, 05/10/2011 - 23:27 62
by c0d1f1ed
Fri, 07/01/2011 - 03:59
Normal topic Why weren't PINSR* instructions extended to 256-bits in AVX2
by perfwise
Tue, 08/27/2013 - 20:24 3
by perfwise
Fri, 08/30/2013 - 06:06
Normal topic Estimating of interrupt latency on the x86 CPUs
by zarathu5tra
Sat, 07/16/2011 - 04:57 0
by zarathu5tra
Sat, 07/16/2011 - 04:57
Normal topic How long does a 6700K take to multiply two integers?
by Nosh N.
Fri, 11/06/2015 - 10:13 3
by iliyapolak
Tue, 12/15/2015 - 09:18
Normal topic SSE3 critique
by Deleted User
Fri, 08/19/2005 - 08:35 3
by Igor Levicki
Tue, 05/27/2008 - 09:59
Normal topic PUSH and POP of XMM/YMM registers
by srinivasu
Wed, 06/18/2014 - 04:57 8
by iliyapolak
Thu, 06/19/2014 - 05:42
Normal topic Illegal Instruction -- Intel SDE with AES instructions
by rksm
Tue, 12/01/2009 - 07:58 3
by Mark Charney (Intel)
Tue, 12/01/2009 - 07:58
Normal topic avx instruction choice
by zhangxiuxia
Mon, 02/20/2012 - 04:55 9
by Max Locktyukhin...
Wed, 02/22/2012 - 18:41
Normal topic RDRAND instruction supported but DRNG not supported
by SathyaShankar K.
Mon, 08/08/2016 - 23:57 1
by Mark Charney (Intel)
Tue, 08/23/2016 - 08:09
Hot topic How many MMX/SSE units in Core-2 Quad
by murzik
Mon, 08/25/2008 - 09:03 31
by iliyapolak
Mon, 03/30/2015 - 23:25
New posts
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Hot topic with new posts
Hot topic without new posts
Sticky topic
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For more complete information about compiler optimizations, see our Optimization Notice.