Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic startersort ascending Post date Replies Last Post
Normal topic x87 and out-of-order execution
by k_sarnath
Wed, 03/31/2010 - 22:33 2
by k_sarnath
Wed, 03/31/2010 - 22:33
Normal topic x64/ia64 Assemly Instructions in Code Porting
by gangti
Wed, 07/01/2009 - 20:18 3
by jimdempseyatthecove
Wed, 07/01/2009 - 20:18
Normal topic x64 Intrinsic Reference
by inteleverywhere
Wed, 06/23/2010 - 22:43 3
by matthieu.darbois
Wed, 06/23/2010 - 22:43
Normal topic Wrong memory size for VGATHERQPS (?)
by Michael R.
Wed, 07/29/2015 - 13:52 1
by Mark Charney (Intel)
Wed, 07/29/2015 - 14:47
Normal topic Working assembly example for MPX?
by c_43
Wed, 07/09/2014 - 10:58 2
by c_43
Thu, 07/10/2014 - 08:40
Normal topic with _mm256 instruction, does it matter to use -xAVX to compiler?
by zlw
Fri, 05/10/2013 - 16:21 12
by Tim P.
Tue, 05/14/2013 - 05:02
Normal topic Wired tsx behavior
by YangHun P.
Sat, 05/21/2016 - 08:06 2
by Roman Dementiev...
Mon, 05/23/2016 - 02:37
Normal topic Will AVX-512 replace the need for dedicated GPU's?
by Christopher H.
Mon, 01/13/2014 - 01:44 13
by iliyapolak
Fri, 01/24/2014 - 12:28
Normal topic Will access and checks through segment register incur more overhead?
by claw L.
Sun, 03/05/2017 - 16:54 2
by Sergey Kostrov
Mon, 03/06/2017 - 10:07
Hot topic Will a vector version of rol be supported in the future
by STEPHEN H.
Thu, 06/16/2016 - 06:55 16
by jimdempseyatthecove
Fri, 08/05/2016 - 07:54
Normal topic Will a vector version of rol be supported in the future
by fafcv z.
Tue, 06/28/2016 - 22:14 1
by jimdempseyatthecove
Wed, 06/29/2016 - 05:05
Normal topic Wierd instruction: extractps
by zhangxiuxia
Fri, 04/20/2012 - 04:33 3
by bronxzv
Sun, 05/27/2012 - 01:53
Normal topic Why weren't PINSR* instructions extended to 256-bits in AVX2
by perfwise
Tue, 08/27/2013 - 20:24 3
by perfwise
Fri, 08/30/2013 - 06:06
Normal topic Why we didn't learn about this here on the ISN first?
by Igor Levicki
Thu, 02/19/2009 - 00:17 2
by Igor Levicki
Thu, 02/19/2009 - 00:17
Normal topic Why this AVX code is slower than SSE?
by zlw
Wed, 09/28/2011 - 21:36 7
by zlw
Tue, 11/08/2011 - 11:09
Normal topic Why the restricted transaction has conflict abort even run a single thread?
by zhaoguo w.
Mon, 06/24/2013 - 05:45 12
by Roman Dementiev...
Tue, 06/25/2013 - 07:17
Normal topic Why the datasheet is incomplete?
by logicman112
Sun, 09/26/2010 - 04:44 0
by logicman112
Sun, 09/26/2010 - 04:44
Normal topic Why only CS, IP and EFLAGS are saved while interrupt??
by cgopi24
Fri, 09/25/2009 - 09:29 1
by Shih Kuo (Intel)
Fri, 10/16/2009 - 01:34
Hot topic Why no FMA in AVX in Sandy Bridge?
by Igor Levicki
Mon, 10/06/2008 - 12:56 18
by tthsqe
Sat, 09/05/2009 - 19:02
Normal topic why is ‘_mm512d load/store’ intrinsic changed to vmovups not vmovupd?
by Yeongha L.
Sun, 02/12/2017 - 23:09 1
by McCalpin, John
Mon, 02/13/2017 - 09:29
Normal topic Why is my AVX slower than SSE?
by Shaquille W.
Tue, 06/02/2015 - 09:18 3
by Tim P.
Wed, 06/10/2015 - 12:59
Hot topic Why is Intel allowing this?!?
by Igor Levicki
Fri, 04/14/2017 - 17:01 32
by Gregg S. (Intel)
Wed, 05/17/2017 - 02:01
Normal topic Why FMA is slower than SSE here?
by Daniel F.
Fri, 12/16/2016 - 02:23 4
by McCalpin, John
Thu, 01/26/2017 - 13:23
Normal topic why does _mm_mulhrs_epi16() always do biased rounding to positive infinity?
by unclejoe
Fri, 01/30/2015 - 19:25 9
by iliyapolak
Fri, 02/06/2015 - 12:07
Normal topic Why AVX do not support real/V86 mode
by yuhong2
Thu, 04/23/2009 - 23:44 1
by Thai Le (Intel)
Thu, 04/23/2009 - 23:44
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For more complete information about compiler optimizations, see our Optimization Notice.