Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

 
Topic / Topic starter Post datesort descending Replies Last Post
Normal topic Weeks of optimizations and still can't beat the intel compiler
by mr_nuke
Fri, 02/19/2010 - 08:34 9
by tthsqe
Fri, 02/19/2010 - 08:38
Normal topic does pentium E5300 have 2 physical cores ?
by ilbeydinler
Thu, 02/25/2010 - 13:13 2
by ilbeydinler
Thu, 02/25/2010 - 14:00
Normal topic Update Bios lennovo t400
by hoapq
Thu, 02/25/2010 - 23:29 1
by Thomas Willhalm...
Thu, 02/25/2010 - 23:29
Normal topic Xed / Objdump errors in disassembly of Intel compiled executables...
by twilkens
Fri, 02/26/2010 - 16:56 2
by twilkens
Fri, 02/26/2010 - 16:56
Normal topic About the x64 stack Alignment
by xfcyhuang
Sun, 02/28/2010 - 10:23 5
by neerajsi_msft
Sun, 02/28/2010 - 15:06
Normal topic AVX/YMM registers and Win64 ABI
by yuhong2
Thu, 03/04/2010 - 17:04 4
by neerajsi_msft
Fri, 03/05/2010 - 09:01
Normal topic Intel I7 - 860 help.
by chadr
Mon, 03/08/2010 - 08:33 2
by Tim Prince
Mon, 03/08/2010 - 08:33
Normal topic Intel(R) SDE release 3.09
by Mark Charney (Intel)
Fri, 03/12/2010 - 18:28 0
by Mark Charney (Intel)
Fri, 03/12/2010 - 18:28
Normal topic Blocks in mix output truncated at 70 instructions..
by perfwise
Sat, 03/13/2010 - 21:18 5
by Mark Charney (Intel)
Sat, 03/13/2010 - 21:18
Normal topic _mm_clmulepi64_si128 pclmulqdq emulation
by Cryptographer
Sat, 03/20/2010 - 01:29 2
by Thomas Willhalm...
Mon, 03/22/2010 - 00:50
Normal topic help on xed in avx package
by jnzhoun
Tue, 03/23/2010 - 21:20 3
by smith001
Tue, 03/23/2010 - 21:20
Normal topic x87 and out-of-order execution
by k_sarnath
Wed, 03/31/2010 - 22:33 2
by k_sarnath
Wed, 03/31/2010 - 22:33
Normal topic Does LBR_SELECT apply to BTF?
by tarmeneldur
Fri, 04/02/2010 - 11:20 2
by tarmeneldur
Fri, 04/02/2010 - 11:24
Normal topic LBR_SELECT in Nehalem - strange behaviour
by tarmeneldur
Wed, 04/07/2010 - 11:47 0
by tarmeneldur
Wed, 04/07/2010 - 11:50
Normal topic Cycle counts of the new Westmere instructions
by Cryptographer
Tue, 04/13/2010 - 00:10 2
by neni
Tue, 04/13/2010 - 00:10
Normal topic Need You Help For My Intel P C
by jackdalson
Wed, 04/21/2010 - 06:21 1
by Thomas Willhalm...
Wed, 04/21/2010 - 06:21
Normal topic Performance of SHA-3 hash functions on Intel processors (Core 2 platform vs Itanium)
by gligoroski
Wed, 04/21/2010 - 07:18 1
by gligoroski
Wed, 04/21/2010 - 07:20
Normal topic SDE disassembly and MS windows disassembly discrepencies
by perfwise
Fri, 04/23/2010 - 14:34 5
by bronxzv
Fri, 04/23/2010 - 14:34
Normal topic SDE execution Error (April, 29, 2010)
by inteleverywhere
Wed, 04/28/2010 - 22:46 8
by bronxzv
Fri, 04/30/2010 - 09:19
Normal topic Processor Cycle and Execution Time of Instruction
by dave1024
Sun, 05/02/2010 - 22:59 2
by Roman Dementiev...
Sun, 05/02/2010 - 23:02
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For more complete information about compiler optimizations, see our Optimization Notice.