Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic Can MPI based application be run on SDE ?
by jnzhoun
Thu, 01/28/2010 - 23:44 3
by jnzhoun
Thu, 01/28/2010 - 23:44
Normal topic Instruction decoder
by rediclo
Tue, 02/10/2009 - 09:06 3
by c0d1f1ed
Tue, 02/10/2009 - 09:06
Normal topic Is PTWRITE and POWERSTAT Packets supported on 7th core processor?
by claw L.
Thu, 04/20/2017 - 08:53 3
by gaston-hillar
Thu, 04/20/2017 - 20:22
Normal topic about partial register stalls
by hurricanezhb
Sat, 04/04/2009 - 00:45 3
by srimks
Sat, 04/04/2009 - 00:45
Normal topic Copy and modify
by sirrida
Tue, 05/10/2011 - 15:59 3
by sirrida
Tue, 05/10/2011 - 15:59
Normal topic where can i find the whole instruction set of sandybridge?
by Lin W.
Mon, 12/10/2012 - 00:41 3
by iliyapolak
Sat, 01/05/2013 - 22:53
Normal topic Extract non-zero byte from _m128i
by Ravi K.
Sat, 05/16/2015 - 16:14 3
by Ravi K.
Mon, 05/25/2015 - 07:29
Normal topic Binary operations per clock cycle in Intel Xeon Phi processors.
by Yash Akhauri
Fri, 09/22/2017 - 08:51 3
by jimdempseyatthecove
Mon, 09/25/2017 - 10:47
Normal topic Why is my AVX slower than SSE?
by Shaquille W.
Tue, 06/02/2015 - 09:18 3
by Tim P.
Wed, 06/10/2015 - 12:59
Normal topic Reversing (V)MOVMSKPS (restoring masks from GPR to XMM / YMM)
by Ralf Karrenberg
Fri, 06/03/2011 - 06:14 3
by bronxzv
Fri, 06/03/2011 - 06:14
Normal topic I want a report about Intel Xeon microprocessor
by wessambasil
Thu, 01/12/2012 - 04:18 3
by Thomas Willhalm...
Fri, 01/13/2012 - 01:21
Normal topic Almost-unit-stride stores
by Fabio L.
Mon, 07/01/2013 - 09:21 3
by jimdempseyatthecove
Thu, 07/18/2013 - 07:40
Normal topic Larrabee docs
by Wolfgang Bauer
Wed, 06/02/2010 - 01:56 3
by knujohn4
Wed, 06/02/2010 - 01:56
Normal topic How to generate the SIGSTRUCT and EINITTOKEN for Intel SGX EINIT instruction?
by gu j.
Wed, 12/23/2015 - 02:46 3
by Simon Johnson (...
Mon, 01/04/2016 - 13:34
Normal topic SIMD instruction thoughput observations..
by perfwise
Thu, 08/19/2010 - 15:14 3
by perfwise
Mon, 08/23/2010 - 11:21
Normal topic SDE - how to run multi-threaded programs with 2MB TLB..
by twilkens
Tue, 06/09/2009 - 09:00 3
by Dny
Tue, 06/09/2009 - 09:00
Normal topic Processing of data in SSE/AVX/AVX2
by Samuel Š.
Thu, 10/30/2014 - 04:58 3
by Tim P.
Sun, 11/23/2014 - 04:16
Normal topic SSE and sorting
by mrosenrosen
Tue, 02/24/2009 - 20:27 3
by Igor Levicki
Wed, 02/25/2009 - 17:13
Normal topic Non-AVX opcodes
by aorl
Fri, 07/30/2010 - 09:12 3
by knujohn4
Sat, 08/07/2010 - 09:42
Normal topic what micro-operations (uops) instruction decoded?
by zhangxiuxia
Wed, 05/18/2011 - 07:33 3
by iliyapolak
Mon, 09/23/2013 - 07:24
Normal topic How to access Cache memory
by suraj_pune
Mon, 01/19/2009 - 04:12 3
by delacy, david
Mon, 01/19/2009 - 04:12
Normal topic load and loadu - alignment
by Christian M.
Tue, 01/08/2013 - 04:57 3
by Christian M.
Fri, 01/11/2013 - 07:21
Normal topic Penealty when mixing AVX and SSE
by maxmus
Thu, 06/16/2011 - 09:15 3
by Brijender Bhart...
Thu, 06/16/2011 - 13:58
Normal topic Popcount emulation for x64 process - RAM memory limit
by Jon D.
Tue, 05/23/2017 - 06:46 3
by Sergey Kostrov
Wed, 05/31/2017 - 08:55
Normal topic Are instruction ups of an instruction be issued at the same time ?
by zhangxiuxia
Thu, 03/08/2012 - 00:00 3
by zhangxiuxia
Tue, 03/13/2012 - 00:54
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For more complete information about compiler optimizations, see our Optimization Notice.