Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

Topic / Topic starter Post date Replies Last Post
Normal topic movd instruction not working with Masm 8.0
by slider77
Wed, 07/22/2009 - 14:04 1
by mazegen
Wed, 07/22/2009 - 14:04
Normal topic Implementation of Software Prefetching Hints
by xift
Wed, 06/23/2010 - 00:21 0
by xift
Wed, 06/23/2010 - 00:21
Normal topic Penealty when mixing AVX and SSE
by maxmus
Thu, 06/16/2011 - 09:15 3
by Brijender Bhart...
Thu, 06/16/2011 - 13:58
Normal topic Problem in compiling SSSE3 in Ubuntu12.04LTS
by Hari K.
Mon, 03/18/2013 - 23:08 9
by Sergey Kostrov
Wed, 03/20/2013 - 05:29
Normal topic Inline asm
by srimks
Mon, 08/10/2009 - 05:00 3
by srimks
Mon, 08/10/2009 - 05:00
Normal topic What's the best way to sum up values in __m128 ?
by zlw
Thu, 02/10/2011 - 15:23 1
by Matthias Kretz
Thu, 02/10/2011 - 15:23
Normal topic Is there an error in Operation pseudo-code for FSIN instruction?
by Sergey Kostrov
Mon, 07/23/2012 - 16:20 1
by iliyapolak
Mon, 07/23/2012 - 17:07
Normal topic Disable SSE* instructions
by Hsunwei H.
Mon, 06/16/2014 - 21:56 6
by John D. McCalpin
Wed, 06/18/2014 - 07:02
Normal topic gcc and avx
by anuj.goyal@gmail.com
Sun, 04/20/2008 - 16:51 2
by srimks
Sun, 04/20/2008 - 16:51
Normal topic x87 and out-of-order execution
by k_sarnath
Wed, 03/31/2010 - 22:33 2
by k_sarnath
Wed, 03/31/2010 - 22:33
Normal topic Function declaration parameters - asm.
by srimks
Mon, 05/18/2009 - 00:40 2
by srimks
Mon, 05/18/2009 - 00:40
Normal topic Compiling with AES-NI in MS Visual Studio 2008/2010
by e.wang
Thu, 10/14/2010 - 13:07 1
by Juan Rodriguez ...
Thu, 10/14/2010 - 13:07
Normal topic Are instruction ups of an instruction be issued at the same time ?
by zhangxiuxia
Thu, 03/08/2012 - 00:00 3
by zhangxiuxia
Tue, 03/13/2012 - 00:54
Normal topic Instruction set extensions programming reference, revision 17,
by Mark Charney (Intel)
Wed, 12/04/2013 - 10:01 13
by avk
Mon, 09/29/2014 - 09:33
Normal topic Alignment requirements for _mm256_maskload_pd
by Stephen G.
Mon, 05/11/2015 - 00:41 7
by Christian M.
Wed, 05/20/2015 - 00:26
Normal topic REAL(16) - long double
by jimdempseyatthecove
Fri, 02/06/2009 - 07:41 9
by jimdempseyatthecove
Wed, 02/11/2009 - 12:14
Normal topic aligniing 'btr' or its address using declspec(align(16))
by Smart Lubobya
Fri, 08/06/2010 - 05:41 8
by Brijender Bhart...
Thu, 08/12/2010 - 10:56
Normal topic Rotate shift in AVX and SSE
by Pourya Shirazian
Thu, 11/10/2011 - 13:57 2
by jimdempseyatthecove
Sat, 11/12/2011 - 14:27
Hot topic Question about example on Optimization manual---AVX mask move to avoid branch penalty
by Deyang Gu
Tue, 06/25/2013 - 11:07 31
by jimdempseyatthecove
Sat, 07/27/2013 - 06:53
Normal topic Could intel somehow initiate migration/cleanup for x86 instruction set?
by htuh
Thu, 11/12/2009 - 16:13 0
by htuh
Tue, 01/12/2010 - 10:45
Normal topic load and loadu - alignment
by Christian M.
Tue, 01/08/2013 - 04:57 3
by Christian M.
Fri, 01/11/2013 - 07:21
Normal topic Intel MPX, gcc/as fail to build glibc
by c_43
Tue, 12/16/2014 - 06:33 2
by c_43
Thu, 01/01/2015 - 23:22
Normal topic adding or comapring 8 bit unsigned data in XMM register
by biplabraut
Mon, 07/28/2008 - 23:17 3
by biplabraut
Mon, 07/28/2008 - 23:17
Normal topic Efficient ways to count setted bits in bytes/words?
by q w.
Tue, 01/22/2013 - 18:48 9
by Sergey Kostrov
Fri, 01/25/2013 - 07:15
Normal topic Interpreting Intel SDE avx/sse transition tracker
by Bram S.
Thu, 01/08/2015 - 12:25 1
by Mark Charney (Intel)
Thu, 01/08/2015 - 12:39
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For more complete information about compiler optimizations, see our Optimization Notice.