Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic what micro-operations (uops) instruction decoded?
by zhangxiuxia
Wed, 05/18/2011 - 07:33 3
by iliyapolak
Mon, 09/23/2013 - 07:24
Normal topic load and loadu - alignment
by Christian M.
Tue, 01/08/2013 - 04:57 3
by Christian M.
Fri, 01/11/2013 - 07:21
Normal topic Penealty when mixing AVX and SSE
by maxmus
Thu, 06/16/2011 - 09:15 3
by Brijender Bhart...
Thu, 06/16/2011 - 13:58
Normal topic How do you move 128-bit value to a new 258-bit register to both lanes?
by gabest
Tue, 06/18/2013 - 10:31 3
by bronxzv
Tue, 06/18/2013 - 13:16
Normal topic Are instruction ups of an instruction be issued at the same time ?
by zhangxiuxia
Thu, 03/08/2012 - 00:00 3
by zhangxiuxia
Tue, 03/13/2012 - 00:54
Normal topic Popcount emulation for x64 process - RAM memory limit
by Jon D.
Tue, 05/23/2017 - 06:46 3
by Sergey Kostrov
Wed, 05/31/2017 - 08:55
Normal topic AVX slowdown using multicores
by gilrgrgmail.com
Sun, 04/17/2011 - 01:21 3
by jimdempseyatthecove
Tue, 04/26/2011 - 07:56
Normal topic About shufps instruction
by Yunqi Z.
Sun, 05/12/2013 - 11:26 3
by Yunqi Z.
Sun, 05/12/2013 - 19:32
Normal topic Extracting XMM register elements gives compilation error
by biplabraut
Mon, 07/28/2008 - 00:31 3
by Igor Levicki
Mon, 07/28/2008 - 00:31
Normal topic How can i disable haswell cache prefetcher?
by zhaoguo w.
Sat, 06/22/2013 - 06:54 3
by iliyapolak
Fri, 02/07/2014 - 02:42
Normal topic _mm_clmulepi64_si128 pclmulqdq emulation
by Cryptographer
Sat, 03/20/2010 - 01:29 3
by David L.
Thu, 10/02/2014 - 15:44
Normal topic Broken links for MPX GCC version on the Intel server?
by c_43
Mon, 06/02/2014 - 09:15 3
by c_43
Fri, 10/10/2014 - 06:40
Normal topic TSX with Haswell-E
by code p.
Sat, 09/06/2014 - 11:51 3
by Roman Dementiev...
Fri, 09/12/2014 - 07:38
Normal topic what type of NMI can trigger VMX NMI exiting
by Tao W.
Thu, 02/16/2017 - 20:39 3
by Tao W.
Wed, 03/01/2017 - 00:37
Normal topic inc/dec instruction vs macrofusion
by Monti, Marco
Sun, 01/20/2013 - 08:00 3
by Tim P.
Mon, 01/21/2013 - 05:48
Normal topic SSE 4.2 on which processors?
by md_intel
Thu, 07/31/2008 - 23:08 3
by Thai Le (Intel)
Thu, 07/31/2008 - 23:08
Normal topic x64 Intrinsic Reference
by inteleverywhere
Wed, 06/23/2010 - 22:43 3
by matthieu.darbois
Wed, 06/23/2010 - 22:43
Normal topic Opcode semantics
by matt.j
Thu, 08/13/2009 - 18:24 3
by c0d1f1ed
Mon, 11/02/2009 - 00:38
Normal topic What is syntax for broadcast decorator?
by Michael R.
Sun, 07/26/2015 - 17:51 3
by Alexander F. (Intel)
Thu, 07/30/2015 - 10:49
Normal topic Wierd instruction: extractps
by zhangxiuxia
Fri, 04/20/2012 - 04:33 3
by bronxzv
Sun, 05/27/2012 - 01:53
Normal topic Assemblers for the new instructionsets
by Paul C.
Tue, 12/04/2012 - 03:30 3
by Tim P.
Tue, 12/04/2012 - 07:31
Normal topic FMA Support
by rmendes.silva
Sun, 03/23/2014 - 12:20 3
by iliyapolak
Mon, 03/24/2014 - 10:46
Normal topic error C2677: binary '[' : no global operator found which takes type '__m128i'
by Smart Lubobya
Thu, 07/01/2010 - 03:15 3
by Brijender Bhart...
Fri, 07/02/2010 - 10:51
Normal topic SSE4 is there a BigInt LIbrary?
by gbrun
Wed, 10/12/2011 - 21:03 3
by styc
Fri, 10/14/2011 - 22:35
Normal topic Is there some instruction to do shift to left by the number from mask register somehow?
by denbianh
Wed, 12/19/2012 - 00:00 3
by denbianh
Wed, 12/26/2012 - 20:49
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For more complete information about compiler optimizations, see our Optimization Notice.