Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic Prologue & Epilogue Help
by srimks
Mon, 08/10/2009 - 01:38 0
by srimks
Mon, 08/10/2009 - 01:38
Normal topic Problem with SSE2 code
by ijjys
Fri, 09/18/2009 - 11:06 0
by ijjys
Fri, 09/18/2009 - 11:06
Normal topic Compiler optimization for SSE4.2 and AVX
by Tim P.
Wed, 05/20/2009 - 10:24 0
by Tim P.
Wed, 05/20/2009 - 10:24
Normal topic Intel® Software Development Emulator, Release 6.12
by Ady Tal (Intel)
Wed, 12/04/2013 - 06:08 0
by Ady Tal (Intel)
Wed, 12/04/2013 - 06:08
Normal topic Doubt in calculating CPIexe
by gokussj9
Mon, 09/13/2010 - 14:39 0
by gokussj9
Mon, 09/13/2010 - 14:39
Normal topic Instruction decoder
by rediclo
Tue, 02/10/2009 - 09:06 0
by rediclo
Tue, 02/10/2009 - 09:06
Normal topic Low rate on sse2 code
by maa1
Mon, 11/23/2009 - 11:39 0
by maa1
Mon, 11/23/2009 - 11:39
Normal topic QPI will abort TSX transactions?
by Oliver K.
Sat, 04/15/2017 - 22:28 0
by Oliver K.
Sat, 04/15/2017 - 22:28
Normal topic Proposal: Push effective address
by sirrida
Wed, 05/11/2011 - 14:51 0
by sirrida
Wed, 05/11/2011 - 14:51
Normal topic C-State Configuration
by rdmsr64
Thu, 05/12/2011 - 04:49 0
by rdmsr64
Thu, 05/12/2011 - 04:49
Normal topic Intel please update hard copy manuals @ lulu.com
by Russell Van Zandt
Mon, 07/24/2017 - 15:49 0
by Russell Van Zandt
Mon, 07/24/2017 - 15:49
Normal topic Are FMA instructions supported with the intel compiler?
by rlaouenan
Tue, 06/01/2010 - 04:17 0
by rlaouenan
Tue, 06/01/2010 - 04:17
Normal topic probable mistake in documentation---please check3
by logicman112
Tue, 09/21/2010 - 00:13 0
by logicman112
Tue, 09/21/2010 - 00:13
Normal topic How does address be mapped onto a memory bank
by zhangyihere
Tue, 12/01/2009 - 02:04 0
by zhangyihere
Tue, 12/01/2009 - 07:30
Normal topic What is behavior of LD + OP instruction with register source and EVEX.b = 1?
by Michael R.
Thu, 09/10/2015 - 00:44 0
by Michael R.
Thu, 09/10/2015 - 00:44
Normal topic Documentation bug for DIV/IDIV
by sirrida
Sat, 07/19/2014 - 10:23 0
by sirrida
Sat, 07/19/2014 - 10:23
Normal topic How to speed up this code?
by Alexander L.
Tue, 01/17/2017 - 16:26 0
by Alexander L.
Tue, 01/17/2017 - 16:26
Normal topic ICPC 13.0.2 generates scalar load instead of packed load
by Paul S.
Wed, 01/15/2014 - 01:45 0
by Paul S.
Wed, 01/15/2014 - 01:45
Normal topic the issue about APIC drop msix interrupt
by wei j.
Sun, 06/28/2015 - 18:27 0
by wei j.
Sun, 06/28/2015 - 18:27
Normal topic RDRAND and Ivy Bridge Celerons
by D. Hugh R.
Sat, 05/21/2016 - 08:43 0
by D. Hugh R.
Sat, 05/21/2016 - 08:43
Normal topic FIPS 140-2 and Intel cryptographic implementations
by Ryan
Fri, 08/18/2017 - 11:19 0
by Ryan
Fri, 08/18/2017 - 11:19
Normal topic MPX instructions not in the Appendix A opcode map
by Bea T.
Wed, 07/01/2015 - 14:28 0
by Bea T.
Wed, 07/01/2015 - 14:28
Normal topic Complex multiply–accumulate
by Mathieu Gravey
Mon, 10/23/2017 - 10:12 0
by Mathieu Gravey
Mon, 10/23/2017 - 10:12
Normal topic segment-specific rdpmc counter
by yangulei
Mon, 07/23/2012 - 13:37 0
by yangulei
Mon, 07/23/2012 - 13:37
Normal topic _mm_clmulepi64_si128 and pclmulqdq doc error
by jimdempseyatthecove
Mon, 12/05/2016 - 13:57 0
by jimdempseyatthecove
Mon, 12/05/2016 - 13:57
New posts
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Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.