Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

Topic / Topic starter Post date Replies Last Postsort descending
Normal topic andps vs. andpd vs. pand
by c0d1f1ed
Fri, 09/19/2008 - 04:23 6
by emmetcaulfield
Wed, 10/08/2008 - 05:19
Normal topic Detecting Nehalem CPU
by dark_shikari
Fri, 10/10/2008 - 15:24 5
by Shih Kuo (Intel)
Fri, 10/17/2008 - 18:26
Normal topic Add Instruction PROTD
by sc00bz
Wed, 10/29/2008 - 07:16 2
by Igor Levicki
Thu, 11/06/2008 - 17:16
Normal topic Low Precision VFNMADDSS on SDE(AVX Emulator)
by wowtiger
Tue, 11/11/2008 - 23:36 5
by gabest
Tue, 11/11/2008 - 23:36
Normal topic AMX Analysis - GNU & Intel
by srimks
Sat, 11/08/2008 - 06:14 1
by Tim Prince
Wed, 11/12/2008 - 23:12
Normal topic AVX alignment requirement
by Tim Prince
Sat, 11/15/2008 - 16:00 1
by Mark Buxton (Intel)
Wed, 11/26/2008 - 13:10
Normal topic Help: Vectorization, x87 & SSE2
by srimks
Mon, 12/01/2008 - 04:06 10
by Michael Stoner ...
Mon, 12/01/2008 - 04:06
Normal topic rdtscl measures less clock cycles on AMD
by walla71
Mon, 12/01/2008 - 07:48 1
by Tim Prince
Mon, 12/01/2008 - 08:37
Normal topic Diagnostic testing of CPU and Support Device Architectures
by daryl_langley_4
Mon, 12/01/2008 - 17:06 1
by Thai Le (Intel)
Tue, 12/09/2008 - 13:51
Normal topic pmovzx/pmovsx
by dark_shikari
Sun, 10/12/2008 - 05:36 14
by Igor Levicki
Sat, 12/27/2008 - 19:36
Normal topic About 256 bit registers
by gabest
Fri, 12/19/2008 - 21:31 5
by Igor Levicki
Thu, 01/01/2009 - 01:07
Normal topic Check if a floating point is actually an Integer
by anujgarg2004gma...
Wed, 01/07/2009 - 09:41 9
by Igor Levicki
Wed, 01/07/2009 - 09:41
Normal topic New SIMDLEA Instruction?
by w0wtiger
Sun, 01/11/2009 - 00:52 2
by Max Locktyukhin...
Sun, 01/11/2009 - 00:52
Normal topic New version of Intel(R) SDE posted
by Mark Charney (Intel)
Mon, 01/12/2009 - 06:14 1
by aaron-tersteeg ...
Mon, 01/12/2009 - 06:15
Normal topic How to access Cache memory
by suraj_pune
Mon, 01/19/2009 - 04:12 3
by beerandcandy
Mon, 01/19/2009 - 04:12
Normal topic SSSE3 intrinsics compilation error on x64 VC++ 2005 platform
by biplabraut
Tue, 01/20/2009 - 03:01 1
by gabest
Tue, 01/20/2009 - 03:01
Normal topic assembly program in itanium based systems
by rkraveesh
Tue, 01/27/2009 - 04:03 2
by forzaitalia2010
Tue, 01/27/2009 - 04:03
Normal topic Performance difference between 32bit and 64bit memcpy
by Tim Day
Tue, 01/27/2009 - 06:50 9
by beerandcandy
Tue, 01/27/2009 - 06:50
Normal topic Documentation suggestion
by jimdempseyatthecove
Fri, 02/06/2009 - 07:15 1
by Shih Kuo (Intel)
Fri, 02/06/2009 - 07:15
Normal topic reverse a PMOVMSKB instruction?
by dattrax
Mon, 02/09/2009 - 14:15 4
by Igor Levicki
Mon, 02/09/2009 - 14:15
Normal topic Instruction decoder
by rediclo
Tue, 02/10/2009 - 09:06 0
by rediclo
Tue, 02/10/2009 - 09:06
Normal topic Instruction decoder
by rediclo
Tue, 02/10/2009 - 09:06 3
by c0d1f1ed
Tue, 02/10/2009 - 09:06
Normal topic REAL(16) - long double
by jimdempseyatthecove
Fri, 02/06/2009 - 07:41 9
by jimdempseyatthecove
Wed, 02/11/2009 - 12:14
Normal topic IA32 ISA
by miro5566
Fri, 02/06/2009 - 05:43 5
by Max Locktyukhin...
Sat, 02/14/2009 - 00:12
Normal topic monitor/mwait disabled by IA32_MISC_ENABLES MSR?
by godofpumpkins
Fri, 02/13/2009 - 19:11 3
by Igor Levicki
Sat, 02/14/2009 - 11:02
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For more complete information about compiler optimizations, see our Optimization Notice.