Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

 
Topic / Topic starter Post datesort descending Replies Last Post
Normal topic Is there any methods to see contents in MMX and XMM registers?
by kalven
Mon, 06/30/2008 - 01:43 3
by srimks
Mon, 06/30/2008 - 01:43
Hot topic Detailed info about FTZ & DAZ
by gol
Thu, 07/03/2008 - 01:36 16
by gol
Wed, 07/23/2008 - 05:41
Normal topic SSE 4.1 instructions - DPPS/EXTRACTPS
by vsachde
Sun, 07/06/2008 - 11:50 11
by lxguy
Sun, 07/06/2008 - 11:50
Normal topic P4 stalls for >240 uSec
by stevek999
Fri, 07/11/2008 - 06:28 6
by Igor Levicki
Tue, 08/05/2008 - 05:18
Normal topic Microinstruction Format
by dargueta
Sat, 07/12/2008 - 22:41 4
by dargueta
Tue, 07/15/2008 - 19:50
Normal topic AVX VBROADCAST instructions. Why is register operand not allowed?
by Agner
Mon, 07/14/2008 - 02:52 6
by Shih Kuo (Intel)
Mon, 07/14/2008 - 02:52
Normal topic How is the brandstring formed by BIOSes?
by pgzh
Fri, 07/25/2008 - 15:25 5
by Igor Levicki
Fri, 07/25/2008 - 15:25
Normal topic Extracting XMM register elements gives compilation error
by biplabraut
Mon, 07/28/2008 - 00:31 3
by Igor Levicki
Mon, 07/28/2008 - 00:31
Normal topic adding or comapring 8 bit unsigned data in XMM register
by biplabraut
Mon, 07/28/2008 - 23:17 3
by biplabraut
Mon, 07/28/2008 - 23:17
Normal topic Consecutive load operations results problem
by biplabraut
Tue, 07/29/2008 - 23:34 2
by biplabraut
Tue, 07/29/2008 - 23:34
Normal topic SSE 4.2 on which processors?
by md_intel
Thu, 07/31/2008 - 23:08 3
by Thai Le (Intel)
Thu, 07/31/2008 - 23:08
Normal topic About INstruction Decoder in P4
by biplabraut
Wed, 08/13/2008 - 00:11 1
by Thai Le (Intel)
Wed, 08/13/2008 - 00:11
Hot topic How many MMX/SSE units in Core-2 Quad
by murzik
Mon, 08/25/2008 - 09:03 21
by iliyapolak
Mon, 03/03/2014 - 06:47
Normal topic FMA now an extension of AVX?
by gabest
Wed, 08/27/2008 - 23:58 1
by Thai Le (Intel)
Mon, 09/08/2008 - 09:32
Normal topic Quad precision ?
by tux456
Thu, 08/28/2008 - 08:10 2
by tux456
Thu, 08/28/2008 - 12:54
Normal topic Timing of LPT-port
by ugtehservis
Wed, 09/03/2008 - 23:36 1
by Igor Levicki
Tue, 09/30/2008 - 17:35
Normal topic andps vs. andpd vs. pand
by c0d1f1ed
Fri, 09/19/2008 - 04:23 6
by emmetcaulfield
Wed, 10/08/2008 - 05:19
Normal topic Forums will be read-only 09/24 10PM PST to 09/25 12PM PST
by Intel Software ...
Mon, 09/22/2008 - 11:46 0
by Intel Software ...
Mon, 09/22/2008 - 11:46
Hot topic Why no FMA in AVX in Sandy Bridge?
by Igor Levicki
Mon, 10/06/2008 - 12:56 18
by tthsqe
Sat, 09/05/2009 - 19:02
Normal topic Detecting Nehalem CPU
by dark_shikari
Fri, 10/10/2008 - 15:24 5
by Shih Kuo (Intel)
Fri, 10/17/2008 - 18:26
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For more complete information about compiler optimizations, see our Optimization Notice.