Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

Topic / Topic starter Post date Replies Last Post
Normal topic LBR_SELECT in Nehalem - strange behaviour
by tarmeneldur
Wed, 04/07/2010 - 11:47 0
by tarmeneldur
Wed, 04/07/2010 - 11:50
Normal topic How to access Cache memory
by suraj_pune
Mon, 01/19/2009 - 04:12 2
by Tim Prince
Tue, 03/10/2009 - 15:06
Normal topic movq doesn't work, it never move the data
by hurricanezhb
Wed, 08/03/2011 - 11:04 3
by hurricanezhb
Wed, 08/03/2011 - 11:04
Normal topic MMX intrinsics performed bad
by Smart Lubobya
Tue, 10/19/2010 - 10:27 1
by Thomas Willhalm...
Tue, 10/19/2010 - 10:27
Normal topic LZCNT on Core i7
by craigj0
Mon, 10/12/2009 - 04:29 1
by Mark Charney (Intel)
Mon, 10/12/2009 - 04:29
Hot topic Synchronizing Time Stamp Counter (Page: 1, 2)
by Roman Oderov
Mon, 10/29/2012 - 11:30 76
by Sergey Kostrov
Tue, 05/21/2013 - 07:07
Hot topic AVX-512 expectations
by c0d1f1ed
Fri, 07/26/2013 - 23:24 29
by iliyapolak
Sun, 09/22/2013 - 23:14
Normal topic How does address be mapped onto a memory bank
by zhangyihere
Tue, 12/01/2009 - 02:04 0
by zhangyihere
Tue, 12/01/2009 - 07:30
Normal topic Is there any methods to see contents in MMX and XMM registers?
by kalven
Mon, 06/30/2008 - 01:43 3
by srimks
Mon, 06/30/2008 - 01:43
Normal topic AVX sometimes slower than SSE
by Eric Nuckols
Wed, 05/18/2011 - 12:22 8
by bronxzv
Fri, 05/20/2011 - 17:20
Normal topic SDE 7.15 for Linux has no 64-bit libs
by andysem
Tue, 02/10/2015 - 00:14 3
by andysem
Tue, 02/10/2015 - 23:32
Normal topic seems to be a mistake, regarding manuals, 64 bit push/pop operation
by logicman112
Fri, 08/13/2010 - 21:31 1
by Shih Kuo (Intel)
Fri, 08/13/2010 - 21:31
Normal topic Intel SIMD - Processor Roadmap
by leec
Tue, 07/21/2009 - 23:10 3
by leec
Tue, 07/21/2009 - 23:10
Normal topic Multi-Byte NOP locks up system.
by DF
Tue, 05/22/2012 - 10:36 2
by DF
Tue, 05/22/2012 - 12:15
Normal topic Intel CPU support for real-time OS
by caosun
Thu, 05/16/2013 - 03:14 6
by Sergey Kostrov
Fri, 05/17/2013 - 06:10
Normal topic Idea for a new SIMD instruction
by Igor Levicki
Fri, 01/05/2007 - 20:56 4
by Igor Levicki
Mon, 01/22/2007 - 17:57
Normal topic TSX with Haswell-E
by code p.
Sat, 09/06/2014 - 11:51 3
by Roman Dementiev...
Fri, 09/12/2014 - 07:38
Normal topic AVX Performance Measure
by inteleverywhere
Thu, 06/24/2010 - 05:48 1
by Tim Prince
Thu, 06/24/2010 - 05:48
Normal topic Vectorization - pragma asm interpretation
by srimks
Sat, 04/25/2009 - 18:50 3
by srimks
Sat, 04/25/2009 - 18:50
Normal topic Intel SDE control
by Milan R.
Mon, 10/20/2014 - 11:32 4
by Milan R.
Tue, 10/21/2014 - 04:54
Normal topic MOVD: Zero-extension of general purpose register as destination
by Adam Warner
Mon, 07/12/2010 - 23:41 2
by Adam Warner
Mon, 07/12/2010 - 23:41
Normal topic Defining "Disassembly of section .plt" in C/C++ code
by srimks
Wed, 05/13/2009 - 00:12 5
by Melanie Blower ...
Fri, 05/15/2009 - 07:41
Normal topic AVX2 application released
by bronxzv
Fri, 02/17/2012 - 00:39 1
by Max Locktyukhin...
Wed, 02/22/2012 - 19:01
Normal topic Obtain time stamp disable (TSD) flag in user-mode
by freeze2046
Tue, 03/29/2011 - 05:54 1
by Chris Hooper
Tue, 03/29/2011 - 05:54
Normal topic AVX2 latency
by CHANGJUN Y.
Fri, 02/22/2013 - 00:37 1
by Christian M.
Fri, 02/22/2013 - 02:04
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For more complete information about compiler optimizations, see our Optimization Notice.