Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Post
Normal topic msr for enabling aes-ni instructions
by thome
Sat, 09/04/2010 - 00:52 5
by Nicolae Popovic...
Fri, 11/05/2010 - 04:59
Normal topic P4 stalls for >240 uSec
by stevek999
Fri, 07/11/2008 - 06:28 6
by Igor Levicki
Tue, 08/05/2008 - 05:18
Normal topic Executed instruction not valid for specified chip (PENTIUM4)
by Jeremy W.
Wed, 02/10/2016 - 07:34 2
by Jeremy W.
Sat, 02/13/2016 - 14:06
Normal topic Generating Prefetch Instructions in AVX code...
by twilkens
Thu, 07/30/2009 - 10:49 5
by Martyn Corden (...
Tue, 08/04/2009 - 11:40
Normal topic Fastest way to AND across packed doubles?
by christian.convey
Thu, 01/19/2012 - 06:40 6
by bronxzv
Thu, 01/19/2012 - 09:43
Normal topic ICPC 13.0.2 generates scalar load instead of packed load
by Paul S.
Wed, 01/15/2014 - 01:45 0
by Paul S.
Wed, 01/15/2014 - 01:45
Normal topic MOVD: Zero-extension of general purpose register as destination
by Adam Warner
Mon, 07/12/2010 - 23:41 2
by Adam Warner
Mon, 07/12/2010 - 23:41
Normal topic GCC + static libmpx
by Nick A.
Thu, 03/24/2016 - 19:19 0
by Nick A.
Thu, 03/24/2016 - 19:19
Normal topic Opcode semantics
by matt.j
Thu, 08/13/2009 - 18:24 3
by c0d1f1ed
Mon, 11/02/2009 - 00:38
Normal topic The dawn of the Intel SSE technology
by Sergey Kostrov
Tue, 02/14/2012 - 09:47 3
by iliyapolak
Sun, 12/23/2012 - 06:34
Normal topic Instruction set extensions programming reference, revision 18
by Mark Charney (Intel)
Tue, 02/18/2014 - 05:55 2
by Mark Charney (Intel)
Fri, 06/06/2014 - 20:30
Normal topic error c2664 in sse2
by Smart Lubobya
Thu, 07/22/2010 - 14:00 5
by Brijender Bhart...
Fri, 07/23/2010 - 10:04
Normal topic Intel's IA32/64 bit architecture's instruction set encoding
by postaquestion
Thu, 04/24/2008 - 16:45 4
by Agner
Wed, 08/06/2008 - 02:50
Normal topic How to build the ICC sample code for AVX?
by lychee_intel
Thu, 02/21/2013 - 21:06 1
by Sergey Kostrov
Fri, 02/22/2013 - 20:55
Normal topic Encodings for instructions with {sae} are unclear in the doc
by Michael R.
Wed, 07/22/2015 - 12:23 4
by Mark Charney (Intel)
Wed, 07/22/2015 - 14:05
Normal topic Converting Sandy Bridge TSC to wall clock time
by Chris Hooper
Mon, 04/25/2011 - 01:05 10
by Chris Hooper
Wed, 05/11/2011 - 10:58
Normal topic SDE Message: "No MPX support"
by Markus M.
Mon, 10/05/2015 - 06:11 6
by Markus M.
Mon, 10/05/2015 - 14:45
Normal topic Compiler optimization for SSE4.2 and AVX
by Tim P.
Wed, 05/20/2009 - 10:24 0
by Tim P.
Wed, 05/20/2009 - 10:24
Normal topic Small AVX speedup
by magicfoot
Thu, 09/08/2011 - 12:16 1
by Brijender Bhart...
Thu, 09/08/2011 - 12:35
Normal topic Instruction set extensions programming reference, revision 15
by Mark Charney (Intel)
Tue, 07/23/2013 - 10:45 0
by Mark Charney (Intel)
Tue, 07/23/2013 - 10:45
Hot topic division sse2 intrinsic
by Smart Lubobya
Thu, 05/27/2010 - 06:50 16
by Thomas Willhalm...
Fri, 01/07/2011 - 05:33
Normal topic ALU/CPU Error Detection
by Charles E.
Fri, 11/30/2012 - 04:10 11
by iliyapolak
Wed, 01/30/2013 - 06:09
Normal topic SSE ucomiss/comiss strange behavior
by Naer J.
Wed, 02/04/2015 - 21:25 7
by Naer J.
Thu, 02/05/2015 - 13:57
Normal topic Analyzing Segmented / Linear Address Of A Process
by reverseengineer
Thu, 12/02/2010 - 20:07 1
by Aubrey W. (Intel)
Mon, 12/13/2010 - 14:51
Normal topic Instruction decoder
by rediclo
Tue, 02/10/2009 - 09:06 0
by rediclo
Tue, 02/10/2009 - 09:06
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.