Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic AVX compiler beta
by Mark Charney (Intel)
Fri, 03/06/2009 - 07:51 3
by Roland W. (Intel)
Thu, 05/28/2009 - 13:23
Normal topic Possible bug in SDE - jump with 16-bit operand size
by Michael R.
Tue, 10/20/2015 - 14:00 3
by Mark Charney (Intel)
Wed, 10/21/2015 - 04:58
Normal topic Rasterizer optimization help...
by kevin-bray
Fri, 03/27/2009 - 11:12 3
by kevin-bray
Fri, 04/03/2009 - 14:03
Normal topic Skylake Xeon and AVX-512VL
by Martin Z.
Thu, 02/16/2017 - 00:28 3
by areid
Fri, 02/17/2017 - 00:22
Normal topic how to display output in sse intrinsic codes
by Smart Lubobya
Mon, 05/31/2010 - 02:52 4
by bronxzv
Mon, 05/31/2010 - 02:56
Normal topic Instruction set latency
by sebitab
Thu, 04/16/2009 - 14:51 4
by Tal Uliel (Intel)
Thu, 04/16/2009 - 14:51
Normal topic Where to Find Intel MMX SIMD Examples
by iekpo
Thu, 02/11/2010 - 13:37 4
by iekpo
Fri, 02/19/2010 - 11:46
Normal topic Calculation of Cycles Per Instruction (CPI) for Intel processors.
by anandcta1234
Wed, 06/01/2011 - 08:24 4
by magicfoot
Wed, 06/01/2011 - 08:24
Normal topic Q&A: RDTSC to measure performance of small # of FP calculations
by Intel Software ...
Tue, 11/14/2006 - 22:30 4
by Intel Software ...
Fri, 08/31/2007 - 15:09
Normal topic mitigating permute costs in AVX 256?
by Todd W.
Sun, 01/15/2017 - 09:21 4
by Todd W.
Thu, 01/19/2017 - 18:47
Normal topic _mm_load_ps generates VMOVUPS
by emmanuel.attia
Thu, 09/26/2013 - 05:33 4
by iliyapolak
Thu, 09/26/2013 - 07:21
Normal topic give me a hint,
by jvava
Thu, 02/26/2009 - 03:08 4
by Shih Kuo (Intel)
Thu, 02/26/2009 - 03:08
Normal topic Storing data is bottleneck?
by Arthur U.
Wed, 01/09/2013 - 02:31 4
by McCalpin, John
Tue, 03/04/2014 - 12:18
Normal topic Core2 Quad (S)SSE 3/4
by ocirne94
Sat, 01/23/2010 - 06:52 4
by Tim P.
Sat, 01/23/2010 - 06:52
Normal topic popcnt latency/throughput in 64bits
by matthieu.darbois
Tue, 06/15/2010 - 01:03 4
by matthieu.darbois
Tue, 06/15/2010 - 01:03
Normal topic How to detect New Instruction support in the Haswell/Broadwell generation Intel® Core™ processor family
by Kumar, Amit
Mon, 10/03/2016 - 14:35 4
by andysem
Wed, 10/05/2016 - 05:08
Normal topic Variability in timing measure using RDTSC
by aeric
Thu, 07/15/2010 - 01:50 4
by Victor Pasko (Intel)
Thu, 07/15/2010 - 01:50
Normal topic Scaling TSX to multi-socket systems
by Stephen R.
Tue, 08/05/2014 - 07:47 4
by Stephen R.
Wed, 08/06/2014 - 07:50
Normal topic New extension needed for Maps and Sets
by Mirza H.
Thu, 07/23/2015 - 01:10 4
by jimdempseyatthecove
Thu, 07/30/2015 - 11:41
Normal topic SDE emulation issue
by srinivasu
Thu, 06/05/2014 - 00:30 4
by Mark Charney (Intel)
Mon, 06/09/2014 - 13:21
Normal topic AVX simulator?
by syoyo
Sat, 04/26/2008 - 03:11 4
by syoyo
Sat, 04/26/2008 - 03:11
Normal topic There are something wrong with using svml in inline ASM
by zhang y.
Wed, 03/05/2014 - 22:58 4
by Vladimir Sedach
Sun, 03/09/2014 - 14:43
Normal topic CPUID Signature Values of DisplayFamily_DisplayModel - A new Appendix is Needed in all Intel Manuals
by Sergey Kostrov
Tue, 05/21/2013 - 17:58 4
by iliyapolak
Mon, 06/03/2013 - 22:29
Normal topic Difference using SSE on Intel and AMD processors (?)
by (name withheld)
Sat, 09/16/2006 - 21:11 4
by jimdempseyatthecove
Mon, 09/25/2006 - 14:11
Normal topic looking for information sources on code optimization using the Intel CPU and the MMX/SSE family instruction set
by amoshkov
Fri, 05/09/2008 - 12:21 4
by srimks
Fri, 05/09/2008 - 12:21
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For more complete information about compiler optimizations, see our Optimization Notice.