Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Post
Normal topic AVX intrinsics: strange output with Intel XE 2011
by bronxzv
Fri, 12/16/2011 - 10:48 6
by bronxzv
Wed, 12/21/2011 - 06:00
Normal topic Studying Intel TSX Performance: strange results
by Alexander K.
Mon, 11/11/2013 - 14:13 9
by jimdempseyatthecove
Mon, 12/30/2013 - 05:08
Normal topic SHA Extensions are availabe on which microarchitecture?
by Andreas T.
Tue, 06/14/2016 - 15:00 1
by andysem
Wed, 06/29/2016 - 04:59
Normal topic How to access Cache memory
by suraj_pune
Mon, 01/19/2009 - 04:12 3
by beerandcandy
Mon, 01/19/2009 - 04:12
Normal topic AVX2 support in IACA
by bronxzv
Sat, 01/14/2012 - 04:38 7
by Patrick Konsor ...
Thu, 02/02/2012 - 09:40
Normal topic unaligned loads avx-128 vs. -256
by Tim P.
Sat, 01/04/2014 - 06:00 8
by Sergey Kostrov
Fri, 01/24/2014 - 13:42
Normal topic Bug on elision lock
by Fábio A.
Thu, 08/11/2016 - 19:32 2
by Roman Dementiev...
Fri, 08/12/2016 - 04:17
Normal topic Debugging SSE/SSE2 ?
by gol
Thu, 12/24/2009 - 03:26 10
by gol
Wed, 01/06/2010 - 04:54
Normal topic [smp] processor disabled
by medinad
Thu, 10/15/2009 - 11:12 5
by Igor Levicki
Thu, 10/15/2009 - 11:13
Hot topic How to assign a constant?
by chang-li
Tue, 01/29/2013 - 21:10 46
by chang-li
Tue, 06/18/2013 - 14:58
Normal topic Why is my AVX slower than SSE?
by Shaquille W.
Tue, 06/02/2015 - 09:18 3
by Tim P.
Wed, 06/10/2015 - 12:59
Normal topic SSE4.2 cpuid support found in Pin/SDE on Intel but not on AMD...
by perfwise
Thu, 08/26/2010 - 15:00 3
by Mark Charney (Intel)
Thu, 08/26/2010 - 15:01
Hot topic Detailed info about FTZ & DAZ
by gol
Thu, 07/03/2008 - 01:36 16
by gol
Wed, 07/23/2008 - 05:41
Normal topic 1024 bit AVX
by magicfoot
Sun, 07/24/2011 - 10:54 8
by c0d1f1ed
Thu, 08/18/2011 - 07:55
Normal topic Almost-unit-stride stores
by Fabio L.
Mon, 07/01/2013 - 09:21 3
by jimdempseyatthecove
Thu, 07/18/2013 - 07:40
Normal topic Highest valid sub-leaf index of CPUID(EAX = 0DH)
by Jeremy W.
Fri, 02/05/2016 - 11:09 2
by Jeremy W.
Fri, 02/05/2016 - 11:49
Normal topic movd instruction not working with Masm 8.0
by slider77
Wed, 07/22/2009 - 14:04 2
by Ogilvie, Duncan
Thu, 09/08/2016 - 13:32
Normal topic Problem with _mm_load_si128
by pranith
Thu, 10/11/2012 - 18:07 3
by Sergey Kostrov
Tue, 11/13/2012 - 17:08
Normal topic Early indicators of AVX512 performance on Skylake?
by angus-hewlett
Thu, 12/18/2014 - 03:55 4
by McCalpin, John
Sat, 12/20/2014 - 10:58
Normal topic Data source for intrinsics guide
by Evan N.
Mon, 04/24/2017 - 19:28 13
by Sergey Kostrov
Wed, 04/26/2017 - 07:42
Normal topic SSE instruction error
by inteleverywhere
Mon, 07/12/2010 - 00:38 7
by Arthur Moroz
Mon, 07/12/2010 - 00:38
Normal topic SFENCE and peripheral devices
by dm7
Mon, 10/15/2007 - 01:21 1
by Intel Software ...
Tue, 10/16/2007 - 08:36
Normal topic Proposal: mov small constant
by sirrida
Fri, 05/13/2011 - 00:43 3
by c0d1f1ed
Sun, 05/15/2011 - 17:27
Normal topic Performing a two element broadcast/load in AVX
by Bharat N.
Thu, 03/28/2013 - 21:55 6
by Bharat N.
Sat, 04/06/2013 - 13:37
Normal topic Behavior of some convert instructions with W=1 in non-64-bit mode
by Michael R.
Tue, 09/01/2015 - 17:33 1
by Mark Charney (Intel)
Wed, 09/02/2015 - 04:23
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No new posts
Hot topic with new posts
Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.