Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

 
Topic / Topic startersort descending Post date Replies Last Post
Hot topic Optimize C code by SSE2
by chang-li
Thu, 01/17/2013 - 18:01 19
by Sergey Kostrov
Thu, 01/24/2013 - 17:12
Normal topic Optimizing SSE2 code and beyond...
by srimks
Fri, 09/04/2009 - 04:58 1
by srimks
Fri, 09/04/2009 - 19:51
Normal topic OT what's the number of registers for the Intel Xeon X7542?
by bravegag
Tue, 10/16/2012 - 02:35 2
by Sergey Kostrov
Sat, 11/03/2012 - 15:18
Normal topic Out of order execution
by tthsqe
Thu, 10/15/2009 - 23:53 9
by tthsqe
Thu, 10/15/2009 - 23:53
Normal topic ow to calculate latency and throughput of instruction?
by maa1
Thu, 12/17/2009 - 10:32 2
by maa1
Thu, 12/17/2009 - 10:32
Normal topic P-State invariant TSC on Nehalem platforms with multi-packages
by pisymbol
Wed, 06/02/2010 - 09:04 3
by Igor Levicki
Wed, 06/02/2010 - 09:22
Normal topic P-State transition monitoring
by rdmsr64
Mon, 05/30/2011 - 10:16 5
by mkamruzz
Mon, 05/30/2011 - 10:16
Normal topic P4 stalls for >240 uSec
by stevek999
Fri, 07/11/2008 - 06:28 6
by Igor Levicki
Tue, 08/05/2008 - 05:18
Normal topic Padding does not help AVX
by Fabio L.
Fri, 01/25/2013 - 01:54 1
by Sergey Kostrov
Fri, 01/25/2013 - 06:10
Normal topic PADDW __m128i _mm_add_epi16 ( __m128i a, __m128i b) doubt
by inteleverywhere
Fri, 07/30/2010 - 01:04 1
by Brijender Bhart...
Fri, 07/30/2010 - 10:28
Normal topic Parallel instructions for detecting MSB in array of bytes
by craptacus
Thu, 10/15/2009 - 12:56 6
by bronxzv
Fri, 10/16/2009 - 01:58
Normal topic PCMPESTRI behaviour
by dj_alek
Wed, 09/21/2011 - 00:31 6
by dj_alek
Wed, 11/30/2011 - 06:37
Normal topic PDEP/PEXT operations for AVX
by c0d1f1ed
Tue, 02/19/2013 - 14:17 12
by c0d1f1ed
Tue, 04/02/2013 - 14:00
Normal topic Penalty for 256-bit loads and stores with cache line splits
by jeremyweek
Tue, 05/10/2011 - 08:03 1
by Tim Prince
Tue, 05/10/2011 - 08:03
Normal topic Penealty when mixing AVX and SSE
by maxmus
Thu, 06/16/2011 - 09:15 3
by Brijender Bhart...
Thu, 06/16/2011 - 13:58
Normal topic pentium cache
by luca83
Thu, 03/26/2009 - 01:01 0
by luca83
Thu, 03/26/2009 - 01:01
Normal topic Performance boost is not as expected using SSE intrinsics
by joggingsonggmail.com
Mon, 01/18/2010 - 23:07 6
by bronxzv
Mon, 01/18/2010 - 23:07
Normal topic Performance counter discrepancy? X5650 (Westmere) throttling
by ryancox
Mon, 11/29/2010 - 09:20 0
by ryancox
Mon, 11/29/2010 - 09:20
Normal topic Performance Counters to measure L1, L2 Cache Misses
by xift
Mon, 06/21/2010 - 00:59 11
by k_sarnath
Mon, 06/21/2010 - 01:02
Normal topic Performance difference between 32bit and 64bit memcpy
by Tim Day
Tue, 01/27/2009 - 06:50 9
by beerandcandy
Tue, 01/27/2009 - 06:50
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For more complete information about compiler optimizations, see our Optimization Notice.