Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

 
Topic / Topic starter Post date Replies Last Post
Normal topic MOVAPS alignment problem
by iliyapolak
Thu, 05/17/2012 - 08:31 2
by iliyapolak
Thu, 05/17/2012 - 11:08
Normal topic About shufps instruction
by Yunqi Z.
Sun, 05/12/2013 - 11:26 3
by Yunqi Z.
Sun, 05/12/2013 - 19:32
Normal topic About INstruction Decoder in P4
by biplabraut
Wed, 08/13/2008 - 00:11 1
by Thai Le (Intel)
Wed, 08/13/2008 - 00:11
Normal topic popcnt latency/throughput in 64bits
by matthieu.darbois
Tue, 06/15/2010 - 01:03 4
by matthieu.darbois
Tue, 06/15/2010 - 01:03
Hot topic Sandy Bridge: SSE performance and AVX gather/scatter (Page: 1, 2, 3)
by c0d1f1ed
Tue, 01/04/2011 - 06:23 123
by bronxzv
Tue, 06/25/2013 - 09:43
Normal topic Performance Issues on AVX Instructions
by heiko77
Fri, 11/25/2011 - 04:42 6
by Maxym Dmytryche...
Fri, 12/09/2011 - 14:45
Normal topic determining L1 and L2 cache state
by maamold
Tue, 08/25/2009 - 10:00 0
by maamold
Tue, 08/25/2009 - 10:00
Normal topic Intel manual has some mistakes
by logicman112
Sat, 06/26/2010 - 21:01 1
by logicman112
Sat, 06/26/2010 - 21:01
Hot topic Integer SIMD instructions weirdness -- needs fixing
by Igor Levicki
Thu, 02/03/2011 - 03:20 27
by Igor Levicki
Mon, 03/14/2011 - 08:52
Normal topic Intel Intrinsic Guide problem
by foxtoxer
Mon, 12/26/2011 - 06:15 8
by Patrick Konsor ...
Mon, 02/13/2012 - 09:59
Normal topic clflush over the LAPIC mapping
by kostikbel1
Mon, 09/14/2009 - 07:49 0
by kostikbel1
Mon, 09/14/2009 - 07:49
Normal topic There are something wrong with using svml in inline ASM
by zhang y.
Wed, 03/05/2014 - 22:58 4
by Vladimir Sedach
Sun, 03/09/2014 - 14:43
Normal topic CPU recommendation?
by audiobahn1000
Fri, 05/30/2008 - 03:16 1
by Igor Levicki
Fri, 05/30/2008 - 03:16
Normal topic Cycle counts of the new Westmere instructions
by Cryptographer
Tue, 04/13/2010 - 00:10 2
by neni
Tue, 04/13/2010 - 00:10
Normal topic Instructions Retired Equation
by gokussj9
Fri, 10/01/2010 - 12:38 1
by Thomas Willhalm...
Mon, 10/04/2010 - 01:55
Normal topic Estimating of interrupt latency on the x86 CPUs
by zarathu5tra
Sat, 07/16/2011 - 04:57 0
by zarathu5tra
Sat, 07/16/2011 - 04:57
Normal topic Bus Error
by srimks
Thu, 06/18/2009 - 02:39 3
by srimks
Thu, 06/18/2009 - 05:25
Normal topic Addressing is slow
by 唐黎 唐.
Wed, 11/14/2012 - 16:19 2
by Sergey Kostrov
Thu, 11/15/2012 - 07:30
Normal topic Gather of byte/word with avx2
by derek N.
Fri, 09/06/2013 - 13:35 2
by perfwise
Sun, 10/13/2013 - 08:19
Normal topic Illegal Instruction -- Intel SDE with AES instructions
by rksm
Tue, 12/01/2009 - 07:58 3
by Mark Charney (Intel)
Tue, 12/01/2009 - 07:58
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.