Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Post
Normal topic uops? IA32/Intel64 vs. micro-ops?
by arrazem
Wed, 01/27/2010 - 20:31 4
by Max Locktyukhin...
Wed, 01/27/2010 - 20:31
Normal topic Low Precision VFNMADDSS on SDE(AVX Emulator)
by wowtiger
Tue, 11/11/2008 - 23:36 5
by gabest
Tue, 11/11/2008 - 23:36
Normal topic Intel(R) Software development emulator 4.46 released
by Mark Charney (Intel)
Fri, 12/16/2011 - 07:12 2
by Mark Charney (Intel)
Fri, 11/02/2012 - 13:24
Normal topic Performance penalty for mixed AVX512 code?
by Russell Van Zandt
Sun, 08/24/2014 - 08:17 7
by Russell Van Zandt
Tue, 09/02/2014 - 05:15
Normal topic Slightly OT, but maybe somebody has an idea.
by Alexander L.
Mon, 02/06/2017 - 16:11 7
by andysem
Tue, 02/07/2017 - 07:56
Normal topic Performance Counters to measure L1, L2 Cache Misses
by xift
Mon, 06/21/2010 - 00:59 11
by k_sarnath
Mon, 06/21/2010 - 01:02
Normal topic Defining "Disassembly of section .plt" in C/C++ code
by srimks
Wed, 05/13/2009 - 00:12 5
by Melanie Blower ...
Fri, 05/15/2009 - 07:41
Hot topic Comparing scalar, SSE and AVX basics....poor performances ??
by Joaquin Tarraga
Wed, 06/06/2012 - 01:28 21
by Max Locktyukhin...
Mon, 06/25/2012 - 20:44
Normal topic Intel SDE and Windows 10 Preview
by John D.
Sat, 05/02/2015 - 07:12 2
by MICHAEL G. (Intel)
Sun, 05/03/2015 - 02:13
Normal topic Costs of scatter store
by Johannes P.
Mon, 09/04/2017 - 11:28 1
by andysem
Tue, 09/05/2017 - 01:29
Normal topic Intell compiler 11.1 and AVX
by Ravi Managuli
Wed, 09/08/2010 - 11:48 7
by Kit Chung (Intel)
Tue, 09/14/2010 - 14:49
Normal topic Problem with SSE2 code
by ijjys
Fri, 09/18/2009 - 11:06 0
by ijjys
Fri, 09/18/2009 - 11:06
Normal topic tsod polling in Sandy Bridge
by Brian Stark
Wed, 01/16/2013 - 10:30 1
by Saptarshi S.
Sat, 11/16/2013 - 12:49
Normal topic how to use SSE/AVX to find the array index for element > 0 ?
by admin
Mon, 02/07/2011 - 09:08 5
by admin
Tue, 02/08/2011 - 03:03
Normal topic How can i disable haswell cache prefetcher?
by zhaoguo w.
Sat, 06/22/2013 - 06:54 3
by iliyapolak
Fri, 02/07/2014 - 02:42
Normal topic What is (name withheld)?
by andysem
Wed, 01/20/2016 - 00:48 2
by iliyapolak
Thu, 01/21/2016 - 01:55
Normal topic Anyone thinking of setting low-width integars with high-width integars?
by kalven
Mon, 06/16/2008 - 01:56 2
by kalven
Thu, 06/19/2008 - 18:52
Normal topic AVX trial facility
by magicfoot
Sat, 07/02/2011 - 12:59 1
by sirrida
Sat, 07/02/2011 - 12:59
Normal topic Instruction set extensions programming reference, revision 18
by Mark Charney (Intel)
Tue, 02/18/2014 - 05:55 2
by Mark Charney (Intel)
Fri, 06/06/2014 - 20:30
Normal topic How is the sign bit represented in memory and in the CPU?
by Marcus J.
Tue, 10/04/2016 - 09:34 2
by Marcus J.
Wed, 10/05/2016 - 21:44
Normal topic _mm_clmulepi64_si128 pclmulqdq emulation
by Cryptographer
Sat, 03/20/2010 - 01:29 3
by David L.
Thu, 10/02/2014 - 15:44
Hot topic Software consequences of extending XMM to YMM
by Agner
Wed, 06/18/2008 - 02:33 15
by Lee K. (Intel)
Thu, 06/29/2017 - 18:01
Normal topic Intel MIC(Many Integrated Core)
by zhangxiuxia
Tue, 07/12/2011 - 05:19 10
by Tim P.
Wed, 07/20/2011 - 05:03
Normal topic Loops inside transactional regions in RTM (TSX)
by jsg
Tue, 03/04/2014 - 10:18 2
by jimdempseyatthecove
Fri, 03/07/2014 - 04:10
Normal topic popcount emulated for core2quads
by Axxe F.
Fri, 10/14/2016 - 01:12 1
by andysem
Fri, 10/14/2016 - 09:02
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No new posts
Hot topic with new posts
Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.