Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

 
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic Could intel somehow initiate migration/cleanup for x86 instruction set?
by htuh
Thu, 11/12/2009 - 16:13 0
by htuh
Tue, 01/12/2010 - 10:45
Normal topic TSC Problem
by faball
Fri, 11/27/2009 - 02:52 0
by faball
Mon, 01/11/2010 - 09:36
Normal topic mul instruction latency
by tthsqe
Sat, 01/09/2010 - 22:52 3
by Max Locktyukhin...
Sat, 01/09/2010 - 22:52
Normal topic Debugging SSE/SSE2 ?
by gol
Thu, 12/24/2009 - 03:26 10
by gol
Wed, 01/06/2010 - 04:54
Normal topic question on avx instruction encoding
by tthsqe
Fri, 01/01/2010 - 02:19 9
by mariaosawa
Fri, 01/01/2010 - 02:19
Normal topic ow to calculate latency and throughput of instruction?
by maa1
Thu, 12/17/2009 - 10:32 2
by maa1
Thu, 12/17/2009 - 10:32
Normal topic We need standardization of the x86 instruction set
by Agner
Sat, 12/05/2009 - 09:35 10
by Igor Levicki
Sat, 12/05/2009 - 09:35
Normal topic VEX prefix and ymm state saving support
by yuhong2
Thu, 12/03/2009 - 23:19 1
by Brijender Bhart...
Fri, 12/04/2009 - 09:00
Normal topic Illegal Instruction -- Intel SDE with AES instructions
by rksm
Tue, 12/01/2009 - 07:58 3
by Mark Charney (Intel)
Tue, 12/01/2009 - 07:58
Normal topic How does address be mapped onto a memory bank
by zhangyihere
Tue, 12/01/2009 - 02:04 0
by zhangyihere
Tue, 12/01/2009 - 07:30
Normal topic PTEST improvement?
by Matthias Kretz
Tue, 11/24/2009 - 00:59 1
by Max Locktyukhin...
Tue, 11/24/2009 - 00:59
Normal topic Low rate on sse2 code
by maa1
Mon, 11/23/2009 - 11:39 0
by maa1
Mon, 11/23/2009 - 11:39
Normal topic How many info could I get to estimate DRAM bandwidth?
by hchen229
Tue, 11/17/2009 - 08:17 1
by Roman Dementiev...
Tue, 11/17/2009 - 08:17
Normal topic Understanding my Benchmarks
by Matthias Kretz
Tue, 11/10/2009 - 08:13 5
by Matthias Kretz
Tue, 11/10/2009 - 08:13
Normal topic Why "subq" as allocate by ICC-v10.0 but not as prologue, but ICC-v11.0 uses "pushq" as prologue?
by srimks
Wed, 01/21/2009 - 01:10 3
by Sergey Maslov (...
Mon, 11/02/2009 - 22:18
Normal topic sse4.2 instructions
by westmere
Fri, 05/01/2009 - 16:03 7
by Shih Kuo (Intel)
Mon, 11/02/2009 - 09:54
Normal topic Opcode semantics
by matt.j
Thu, 08/13/2009 - 18:24 3
by c0d1f1ed
Mon, 11/02/2009 - 00:38
Normal topic help on detecting stalls(identifying structural hazards) in assembly code
by ddmetro
Wed, 10/28/2009 - 10:18 1
by Tim Prince
Wed, 10/28/2009 - 10:18
Normal topic is there a standard format in which we provide architecture specific information to a software
by ddmetro
Sun, 10/25/2009 - 16:24 0
by ddmetro
Sun, 10/25/2009 - 16:24
Normal topic how to turn off out-of-order execution in Intel processor
by ddmetro
Sun, 10/25/2009 - 14:32 3
by ddmetro
Sun, 10/25/2009 - 14:32
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For more complete information about compiler optimizations, see our Optimization Notice.