Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

Topic / Topic starter Post datesort descending Replies Last Post
Normal topic Intel CPU support for real-time OS
by caosun
Thu, 05/16/2013 - 03:14 6
by Sergey Kostrov
Fri, 05/17/2013 - 06:10
Hot topic Latency of a General purpose MOV instruction on Intel CPUs
by Sergey Kostrov
Sun, 05/19/2013 - 21:03 22
by Sergey Kostrov
Mon, 05/27/2013 - 05:41
Normal topic CPUID Signature Values of DisplayFamily_DisplayModel - A new Appendix is Needed in all Intel Manuals
by Sergey Kostrov
Tue, 05/21/2013 - 17:58 4
by iliyapolak
Mon, 06/03/2013 - 22:29
Hot topic IB gpr load latency and displacement size
by perfwise
Tue, 05/28/2013 - 06:15 15
by iliyapolak
Tue, 06/04/2013 - 22:10
Normal topic CPU Family and Model
by Bo W.
Mon, 06/03/2013 - 04:15 10
by iliyapolak
Wed, 06/05/2013 - 23:34
Normal topic extremely slow program from using AVX instructions
by unclejoe
Wed, 06/05/2013 - 19:25 9
by Sergey Kostrov
Thu, 06/06/2013 - 22:44
Normal topic Use pointer to __m256 or use _mm256_load_ps
by Nadav S.
Thu, 06/06/2013 - 04:37 10
by jimdempseyatthecove
Mon, 06/10/2013 - 04:40
Normal topic Mixing AVX and MMX code
by Elmar
Fri, 06/07/2013 - 05:05 8
by iliyapolak
Mon, 06/10/2013 - 05:11
Normal topic Function Vectorization
by Vahid N.
Fri, 06/14/2013 - 13:51 10
by Sergey Kostrov
Tue, 06/18/2013 - 16:23
Normal topic Capacity abort when using RTM provided by haswell
by zhaoguo w.
Sat, 06/15/2013 - 01:59 4
by Roman Dementiev...
Tue, 06/25/2013 - 03:48
Normal topic How do you move 128-bit value to a new 258-bit register to both lanes?
by gabest
Tue, 06/18/2013 - 10:31 3
by bronxzv
Tue, 06/18/2013 - 13:16
Hot topic Simple question about single and double float terminology
by magicfoot
Tue, 06/18/2013 - 13:14 25
by iliyapolak
Wed, 05/07/2014 - 11:04
Normal topic Looking for smartest way to insert a DWORD into AVX register
by Elmar
Thu, 06/20/2013 - 05:39 8
by andysem
Tue, 06/25/2013 - 00:30
Normal topic How can i disable haswell cache prefetcher?
by zhaoguo w.
Sat, 06/22/2013 - 06:54 3
by iliyapolak
Fri, 02/07/2014 - 02:42
Normal topic Does the cache prefetcher will abort the rtm transaction?
by zhaoguo w.
Sat, 06/22/2013 - 06:56 5
by John D. McCalpin
Mon, 06/24/2013 - 15:46
Normal topic Why the restricted transaction has conflict abort even run a single thread?
by zhaoguo w.
Mon, 06/24/2013 - 05:45 12
by Roman Dementiev...
Tue, 06/25/2013 - 07:17
Hot topic IPP causes invalid opcode exception at h9_ippsFFTGetSize_C_32fc
by Beni F.
Tue, 06/25/2013 - 06:17 29
by Beni F.
Thu, 06/27/2013 - 10:02
Hot topic Question about example on Optimization manual---AVX mask move to avoid branch penalty
by Deyang Gu
Tue, 06/25/2013 - 11:07 31
by jimdempseyatthecove
Sat, 07/27/2013 - 06:53
Hot topic Haswell GFLOPS (Page: 1, 2)
by caosun
Wed, 06/26/2013 - 02:42 71
by perfwise
Mon, 07/29/2013 - 05:46
Hot topic To use FPU
by GHui
Fri, 06/28/2013 - 02:13 23
by GHui
Thu, 07/11/2013 - 09:27
Normal topic Almost-unit-stride stores
by Fabio L.
Mon, 07/01/2013 - 09:21 3
by jimdempseyatthecove
Thu, 07/18/2013 - 07:40
Hot topic How to extract DWORD from upper half of 256-bit register? (Page: 1, 2)
by Igor Levicki
Tue, 07/02/2013 - 04:51 63
by iliyapolak
Tue, 12/17/2013 - 13:04
Hot topic Haswell TLBs undefined in Intel cpu spec
by perfwise
Tue, 07/02/2013 - 14:37 15
by perfwise
Thu, 10/31/2013 - 13:48
Hot topic SSE4 Register-Handling
by adrian s.
Wed, 07/10/2013 - 07:58 21
by Sergey Kostrov
Thu, 07/18/2013 - 18:38
Normal topic SSE2 vectorized code seems to run slower than non-vectorized code
by tomk@ap.com
Thu, 07/11/2013 - 08:05 12
by iliyapolak
Sun, 07/28/2013 - 02:40
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For more complete information about compiler optimizations, see our Optimization Notice.