Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Post
Normal topic C++-implementation of the Larrabee new instructions
by Thomas Willhalm...
Fri, 04/03/2009 - 02:48 5
by Thomas Willhalm...
Fri, 04/03/2009 - 02:48
Normal topic inc/dec instruction vs macrofusion
by rivet_amber
Sun, 01/20/2013 - 08:00 3
by Tim P.
Mon, 01/21/2013 - 05:48
Normal topic Alignment requirements for _mm256_maskload_pd
by Stephen G.
Mon, 05/11/2015 - 00:41 7
by Christian M.
Wed, 05/20/2015 - 00:26
Normal topic Check arrays for equality with SIMD
by CommanderLake
Thu, 09/14/2017 - 10:28 3
by Tim P.
Sun, 09/17/2017 - 14:05
Normal topic Signed Saturation of integers
by Prashanthns
Fri, 02/11/2011 - 04:39 1
by Max Locktyukhin...
Tue, 03/08/2011 - 08:25
Normal topic Opcode semantics
by matt.j
Thu, 08/13/2009 - 18:24 3
by c0d1f1ed
Mon, 11/02/2009 - 00:38
Normal topic Intel MIC(Many Integrated Core)
by zhangxiuxia
Tue, 07/12/2011 - 05:19 10
by Tim P.
Wed, 07/20/2011 - 05:03
Hot topic IPP causes invalid opcode exception at h9_ippsFFTGetSize_C_32fc
by Beni F.
Tue, 06/25/2013 - 06:17 29
by Beni F.
Thu, 06/27/2013 - 10:02
Normal topic intel xe composer compiler with AVX code
by semsem h.
Mon, 01/25/2016 - 07:21 2
by semsem h.
Tue, 01/26/2016 - 06:13
Normal topic Does LBR_SELECT apply to BTF?
by tarmeneldur
Fri, 04/02/2010 - 11:20 2
by tarmeneldur
Fri, 04/02/2010 - 11:24
Normal topic Intel's IA32/64 bit architecture's instruction set encoding
by postaquestion
Thu, 04/24/2008 - 16:45 4
by Agner
Wed, 08/06/2008 - 02:50
Normal topic CPUID check and CR0 check
by interruptreques...
Fri, 02/17/2012 - 00:51 2
by Sergey Kostrov
Wed, 02/22/2012 - 10:53
Normal topic Loops inside transactional regions in RTM (TSX)
by jsg
Tue, 03/04/2014 - 10:18 2
by jimdempseyatthecove
Fri, 03/07/2014 - 04:10
Normal topic popcount emulated for core2quads
by Axxe F.
Fri, 10/14/2016 - 01:12 1
by andysem
Fri, 10/14/2016 - 09:02
Normal topic Binary operators a%b and a/b in SSE2
by Smart Lubobya
Fri, 07/23/2010 - 08:13 1
by neni
Fri, 07/23/2010 - 08:13
Normal topic rdtscl measures less clock cycles on AMD
by walla71
Mon, 12/01/2008 - 07:48 1
by Tim P.
Mon, 12/01/2008 - 08:37
Normal topic Got BSOD with KeSaveExtendedProcessorState
by David Chou (Intel)
Mon, 08/27/2012 - 18:16 4
by Igor Levicki
Tue, 09/25/2012 - 02:33
Hot topic Indirect Bit Indexing and Set
by Alexander L.
Mon, 12/15/2014 - 07:50 44
by bronxzv
Mon, 12/22/2014 - 17:29
Normal topic QPI will abort TSX transactions?
by Oliver K.
Sat, 04/15/2017 - 22:28 0
by Oliver K.
Sat, 04/15/2017 - 22:28
Normal topic 4K False Store Forwarding...
by Evren Yurtesen
Tue, 10/19/2010 - 05:29 1
by Thomas Willhalm...
Tue, 10/19/2010 - 05:29
Normal topic Compiler optimization for SSE4.2 and AVX
by Tim P.
Wed, 05/20/2009 - 10:24 0
by Tim P.
Wed, 05/20/2009 - 10:24
Hot topic IA32_PERF_CTL on X64 error
by Matt S.
Thu, 02/28/2013 - 08:56 26
by iliyapolak
Mon, 03/18/2013 - 23:39
Normal topic What is syntax for broadcast decorator?
by Michael R.
Sun, 07/26/2015 - 17:51 3
by Alexander F. (Intel)
Thu, 07/30/2015 - 10:49
Normal topic Penalty for 256-bit loads and stores with cache line splits
by jeremyweek
Tue, 05/10/2011 - 08:03 1
by Tim P.
Tue, 05/10/2011 - 08:03
Normal topic AVX in Sandy Bridge
by bronxzv
Wed, 09/23/2009 - 03:30 8
by bronxzv
Wed, 09/23/2009 - 04:48
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.