Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic Missing instruction in SSE: PSLLDQ with _bit_ shift amount?
by geofflangdale
Thu, 02/28/2008 - 15:33 4
by happyIntelCamper
Thu, 02/28/2008 - 15:33
Normal topic Blocks in mix output truncated at 70 instructions..
by perfwise
Sat, 03/13/2010 - 21:18 5
by Mark Charney (Intel)
Sat, 03/13/2010 - 21:18
Normal topic IA32 ISA
by miro5566
Fri, 02/06/2009 - 05:43 5
by Max Locktyukhin...
Sat, 02/14/2009 - 00:12
Normal topic How is the brandstring formed by BIOSes?
by pgzh
Fri, 07/25/2008 - 15:25 5
by Igor Levicki
Fri, 07/25/2008 - 15:25
Normal topic error c2664 in sse2
by Smart Lubobya
Thu, 07/22/2010 - 14:00 5
by Brijender Bhart...
Fri, 07/23/2010 - 10:04
Normal topic float precise
by zhangxiuxia
Wed, 04/18/2012 - 20:33 5
by Sergey Kostrov
Tue, 04/24/2012 - 18:19
Normal topic TSX example code doesn't work
by YangHun P.
Mon, 02/23/2015 - 21:18 5
by jimdempseyatthecove
Thu, 02/26/2015 - 08:11
Normal topic P-State transition monitoring
by rdmsr64
Mon, 05/30/2011 - 10:16 5
by mkamruzz
Mon, 05/30/2011 - 10:16
Normal topic About 256 bit registers
by gabest
Fri, 12/19/2008 - 21:31 5
by Igor Levicki
Thu, 01/01/2009 - 01:07
Normal topic Benefits of SSE/AVX processing when an integrated GPU is missing?
by Toby
Tue, 12/16/2014 - 07:08 5
by Toby
Tue, 12/16/2014 - 09:35
Normal topic Is there some books about SIMD(sse, avx and so on) optimization?
by zhang h.
Tue, 12/17/2013 - 02:08 5
by McCalpin, John
Thu, 04/28/2016 - 08:53
Normal topic Strange IPC behavior
by Patrick P.
Sun, 10/19/2014 - 13:11 5
by Patrick P.
Tue, 10/21/2014 - 04:44
Normal topic SDE disassembly and MS windows disassembly discrepencies
by perfwise
Fri, 04/23/2010 - 14:34 5
by bronxzv
Fri, 04/23/2010 - 14:34
Normal topic About the x64 stack Alignment
by xfcyhuang
Sun, 02/28/2010 - 10:23 5
by neerajsi_msft
Sun, 02/28/2010 - 15:06
Normal topic Adding consecutive large numbers
by Angelos P.
Tue, 04/30/2013 - 06:33 5
by Sergey Kostrov
Thu, 05/02/2013 - 07:31
Normal topic Newbie: SSE with integers
by spertulo
Tue, 11/16/2010 - 01:32 5
by 0xr
Tue, 11/16/2010 - 01:32
Normal topic Intel® Software Development Emulator, Release 5.38
by Mark Charney (Intel)
Fri, 01/04/2013 - 09:25 5
by Sergey Kostrov
Thu, 02/21/2013 - 18:50
Normal topic msr for enabling aes-ni instructions
by thome
Sat, 09/04/2010 - 00:52 5
by Nicolae Popovic...
Fri, 11/05/2010 - 04:59
Normal topic RTM/HLE abort on stack pointer mod
by Oliver K.
Mon, 04/03/2017 - 02:24 5
by Cownie, James H...
Tue, 04/04/2017 - 05:43
Normal topic AVX Base and Turbo Frequencies on non E5 CPUs
by Andrew L.
Mon, 10/19/2015 - 16:22 5
by iliyapolak
Fri, 12/18/2015 - 12:33
Normal topic Does the cache prefetcher will abort the rtm transaction?
by zhaoguo w.
Sat, 06/22/2013 - 06:56 5
by McCalpin, John
Mon, 06/24/2013 - 15:46
Normal topic Intel MPX with i5-6300U processor
by Jeremy W.
Thu, 01/21/2016 - 07:03 5
by Jeremy W.
Mon, 01/25/2016 - 06:42
Normal topic vminpd and vmulpd do run concurrently on Haswell and earlier CPUs
by Bartek S.
Thu, 04/07/2016 - 17:38 5
by Bartek S.
Sat, 04/09/2016 - 05:03
Normal topic Cache and _mm_prefetch
by Christian M.
Sun, 05/10/2015 - 04:10 5
by Vladimir Sedach
Wed, 05/13/2015 - 02:45
Normal topic How to convert two __m256d to one __m512d using intrinsics
by Zekun Y.
Sun, 10/23/2016 - 00:14 5
by areid
Wed, 11/23/2016 - 19:52
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For more complete information about compiler optimizations, see our Optimization Notice.