Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post datesort descending Replies Last Post
Normal topic SIGILL on AVX instruction
by Irfan H.
Mon, 05/12/2014 - 11:18 12
by andysem
Tue, 05/13/2014 - 22:58
Normal topic Intel MPX, unable to reproduce results in example
by c_43
Tue, 05/27/2014 - 11:17 3
by c_43
Mon, 06/02/2014 - 09:43
Normal topic AVX _mm256_store_ps
by lex
Sun, 06/01/2014 - 12:21 11
by emmanuel.attia
Mon, 06/16/2014 - 09:49
Normal topic Broken links for MPX GCC version on the Intel server?
by c_43
Mon, 06/02/2014 - 09:15 3
by c_43
Fri, 10/10/2014 - 06:40
Normal topic SDE emulation issue
by srinivasu
Thu, 06/05/2014 - 00:30 4
by Mark Charney (Intel)
Mon, 06/09/2014 - 13:21
Normal topic Need help: Why my avx code is slower than SSE code?
by Chen S.
Sun, 06/08/2014 - 04:38 8
by emmanuel.attia
Mon, 06/16/2014 - 09:45
Normal topic instructional change __m128i
by lex
Sat, 06/14/2014 - 14:28 1
by Thomas Willhalm...
Sun, 06/15/2014 - 14:55
Normal topic Disable SSE* instructions
by Hsunwei H.
Mon, 06/16/2014 - 21:56 6
by John McCalpin
Wed, 06/18/2014 - 07:02
Normal topic PUSH and POP of XMM/YMM registers
by srinivasu
Wed, 06/18/2014 - 04:57 8
by iliyapolak
Thu, 06/19/2014 - 05:42
Normal topic Intel - Version 19 of ISA Extensions manual available
by Russell Van Zandt
Fri, 06/27/2014 - 16:07 1
by Thomas Willhalm...
Mon, 06/30/2014 - 04:09
Normal topic When is AVX 512 on a chip, not just an emulator?
by Thomas H.
Tue, 07/01/2014 - 05:06 4
by bronxzv
Fri, 08/08/2014 - 04:37
Normal topic Working assembly example for MPX?
by c_43
Wed, 07/09/2014 - 10:58 2
by c_43
Thu, 07/10/2014 - 08:40
Normal topic Documentation bug for DIV/IDIV
by sirrida
Sat, 07/19/2014 - 10:23 0
by sirrida
Sat, 07/19/2014 - 10:23
Normal topic Updated Intel® Software Development Emulator
by Mark Charney (Intel)
Sun, 07/20/2014 - 06:13 7
by andysem
Tue, 11/04/2014 - 14:12
Normal topic Latest GCC to use with the SDE for MPX?
by c_43
Wed, 07/23/2014 - 05:59 1
by Maurious P.
Wed, 07/23/2014 - 06:31
Normal topic BNDLDX/BNDSTX, BNDSTATUS error = 2, expected behavior?
by c_43
Fri, 07/25/2014 - 00:23 3
by MICHAEL B. (Intel)
Wed, 07/30/2014 - 23:56
Normal topic SSE4 Intrensics on Visual Studio 2008
by Uday Krishna G.
Wed, 07/30/2014 - 23:50 6
by Thomas Willhalm...
Fri, 08/01/2014 - 04:53
Normal topic Scaling TSX to multi-socket systems
by Stephen R.
Tue, 08/05/2014 - 07:47 4
by Stephen R.
Wed, 08/06/2014 - 07:50
Normal topic Possible XED Decode Bug (from Pin rev 65163)
by Paul J.
Fri, 08/22/2014 - 13:02 2
by Paul J.
Fri, 08/22/2014 - 14:37
Normal topic Performance penalty for mixed AVX512 code?
by Russell Van Zandt
Sun, 08/24/2014 - 08:17 7
by Russell Van Zandt
Tue, 09/02/2014 - 05:15
Normal topic What is _MM_SHUFFLE macro meaning in the context of AVX
by Hien P.
Tue, 08/26/2014 - 21:44 2
by Hien P.
Wed, 08/27/2014 - 17:28
Normal topic BEXTR intrinsic incompatible with GCC
by Nathan K.
Thu, 08/28/2014 - 11:32 1
by Brandon Hewitt ...
Thu, 08/28/2014 - 13:10
Normal topic TSX with Haswell-E
by code p.
Sat, 09/06/2014 - 11:51 3
by Roman Dementiev...
Fri, 09/12/2014 - 07:38
Normal topic New Xeons on Intel Ark
by emmanuel.attia
Tue, 09/09/2014 - 02:28 9
by Tim P.
Fri, 09/12/2014 - 07:39
Normal topic Penalties in SSE4
by Uday Krishna G.
Thu, 10/09/2014 - 04:30 2
by iliyapolak
Mon, 10/20/2014 - 00:03
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For more complete information about compiler optimizations, see our Optimization Notice.