Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Post
Normal topic andps vs. andpd vs. pand
by c0d1f1ed
Fri, 09/19/2008 - 04:23 6
by emmetcaulfield
Wed, 10/08/2008 - 05:19
Normal topic Minor documentation bugs of movd and movq
by sirrida
Wed, 11/02/2011 - 07:50 1
by Shih Kuo (Intel)
Wed, 11/02/2011 - 07:50
Normal topic P-State invariant TSC on Nehalem platforms with multi-packages
by pisymbol
Wed, 06/02/2010 - 09:04 3
by Igor Levicki
Wed, 06/02/2010 - 09:22
Normal topic do _mm256_load_ps slower than _mm_load_ps?
by zhang h.
Mon, 09/09/2013 - 20:40 14
by Sergey Kostrov
Fri, 11/01/2013 - 14:10
Normal topic PROBLEMS running SDE when submitting request via pbs script on a cluster
by Rohit G.
Wed, 05/18/2016 - 05:45 9
by Rohit G.
Wed, 05/18/2016 - 07:23
Normal topic Vectorization - pragma asm interpretation
by srimks
Sat, 04/25/2009 - 18:50 3
by srimks
Sat, 04/25/2009 - 18:50
Normal topic MOVAPS alignment problem
by iliyapolak
Thu, 05/17/2012 - 08:31 2
by iliyapolak
Thu, 05/17/2012 - 11:08
Normal topic SSE4.2 cpuid support found in Pin/SDE on Intel but not on AMD...
by perfwise
Thu, 08/26/2010 - 15:00 3
by Mark Charney (Intel)
Thu, 08/26/2010 - 15:01
Normal topic Documentation bug for DIV/IDIV
by sirrida
Sat, 07/19/2014 - 10:23 0
by sirrida
Sat, 07/19/2014 - 10:23
Normal topic How to speed up this code?
by Alexander L.
Tue, 01/17/2017 - 16:26 0
by Alexander L.
Tue, 01/17/2017 - 16:26
Normal topic fpu & extended precision - not as accurate as it should be?
by tthsqe
Sun, 08/30/2009 - 22:00 2
by Tim P.
Mon, 08/31/2009 - 05:34
Normal topic Is there some instruction to do shift to left by the number from mask register somehow?
by denbianh
Wed, 12/19/2012 - 00:00 3
by denbianh
Wed, 12/26/2012 - 20:49
Hot topic Mixing SSE and AVX inside an application
by michaelnikelsky
Sun, 01/16/2011 - 03:01 36
by Igor Levicki
Thu, 01/27/2011 - 07:47
Normal topic Can AVX instruction be executed in parallel
by Manish K.
Mon, 03/30/2015 - 03:12 6
by iliyapolak
Tue, 03/31/2015 - 01:11
Normal topic About MONITOR and MWAIT
by Luchezar B.
Fri, 08/04/2017 - 02:01 2
by Luchezar B.
Fri, 08/04/2017 - 04:04
Normal topic crc32 emulation support
by tinman8088
Sun, 05/25/2008 - 21:28 3
by Igor Levicki
Sun, 05/25/2008 - 21:28
Normal topic Weird BTS Performance
by cwillems
Fri, 06/10/2011 - 07:25 5
by Hussam Mousa (Intel)
Fri, 06/10/2011 - 07:25
Normal topic Update Bios lennovo t400
by hoapq
Thu, 02/25/2010 - 23:29 1
by Thomas Willhalm...
Thu, 02/25/2010 - 23:29
Normal topic Mixing AVX and MMX code
by Elmar
Fri, 06/07/2013 - 05:05 8
by iliyapolak
Mon, 06/10/2013 - 05:11
Normal topic Intel TSX-NI with m3-6Y30 processor
by Jeremy W.
Wed, 01/06/2016 - 07:48 1
by Mark Charney (Intel)
Tue, 01/12/2016 - 14:13
Normal topic How to access Cache memory
by suraj_pune
Mon, 01/19/2009 - 04:12 2
by Tim P.
Tue, 03/10/2009 - 15:06
Normal topic Does Intel Software Development Emulator support SSE3 instruction set?
by Sergey Kostrov
Tue, 01/17/2012 - 20:48 5
by Mark Charney (Intel)
Wed, 01/18/2012 - 18:24
Normal topic SSE instruction error
by inteleverywhere
Mon, 07/12/2010 - 00:38 7
by Arthur Moroz
Mon, 07/12/2010 - 00:38
Normal topic Capacity abort when using RTM provided by haswell
by zhaoguo w.
Sat, 06/15/2013 - 01:59 4
by Roman Dementiev...
Tue, 06/25/2013 - 03:48
Normal topic code optimization and vtune
by Zhiyong Z.
Tue, 01/12/2016 - 14:03 8
by iliyapolak
Thu, 01/14/2016 - 09:51
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Hot topic with new posts
Hot topic without new posts
Sticky topic
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For more complete information about compiler optimizations, see our Optimization Notice.