Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Topic / Topic starter Post date Replies Last Post
Normal topic code vectorisation
by Smart Lubobya
Sun, 08/01/2010 - 10:13 1
by Brijender Bhart...
Thu, 08/19/2010 - 17:39
Normal topic Is there any course or example for SSE/MMX beginer ?
by Gaiger Chen
Wed, 11/17/2010 - 19:34 7
by Taronyu
Fri, 11/19/2010 - 05:50
Normal topic Can SSE code conversion be automated
by magicfoot
Fri, 05/20/2011 - 14:35 4
by Hannes Hofmann
Mon, 05/23/2011 - 05:48
Normal topic P4 stalls for >240 uSec
by stevek999
Fri, 07/11/2008 - 06:28 6
by Igor Levicki
Tue, 08/05/2008 - 05:18
Hot topic Haswell RCPPS/RSQRTPS implementation
by maratyszcza
Wed, 05/01/2013 - 16:06 16
by iliyapolak
Wed, 05/08/2013 - 23:47
Normal topic AES-NI performance degraded on SMP, Linux
by Joong
Wed, 11/09/2011 - 05:05 2
by Adrian Hoban (Intel)
Fri, 12/09/2011 - 01:59
Normal topic inter-procedural TSX
by Shu W.
Sun, 03/13/2016 - 21:42 1
by andysem
Mon, 03/14/2016 - 02:14
Normal topic Display problem
by jayarajnayak
Fri, 02/27/2009 - 23:14 2
by coolman010
Fri, 02/27/2009 - 23:14
Hot topic AVX Optimizations and Performance: VisualStudio vs GCC
by James S.
Tue, 10/01/2013 - 18:46 42
by iliyapolak
Fri, 02/21/2014 - 06:38
Hot topic Optimization of sine function's taylor expansion (Page: 1, 2, 3Last Page)
by iliyapolak
Thu, 05/24/2012 - 05:29 342
by iliyapolak
Tue, 12/11/2012 - 23:50
Normal topic mul instruction latency
by tthsqe
Sat, 01/09/2010 - 22:52 3
by Max Locktyukhin...
Sat, 01/09/2010 - 22:52
Normal topic _mm_clmulepi64_si128 and pclmulqdq doc error
by jimdempseyatthecove
Mon, 12/05/2016 - 13:57 0
by jimdempseyatthecove
Mon, 12/05/2016 - 13:57
Normal topic Generating Prefetch Instructions in AVX code...
by twilkens
Thu, 07/30/2009 - 10:49 5
by Martyn Corden (...
Tue, 08/04/2009 - 11:40
Normal topic BNDLDX/BNDSTX, BNDSTATUS error = 2, expected behavior?
by c_43
Fri, 07/25/2014 - 00:23 3
by MICHAEL B. (Intel)
Wed, 07/30/2014 - 23:56
Normal topic Influence of random noise factors on CPU accuracy
by iliyapolak
Sat, 01/05/2013 - 23:09 7
by iliyapolak
Wed, 02/06/2013 - 22:19
Normal topic Intel documentation seems to have wrong or ambiguous information!
by logicman112
Sun, 06/13/2010 - 21:24 1
by mecej4
Sun, 06/13/2010 - 21:24
Normal topic Intel Software Development Emulator for Itanium architecture
by Sergey Kostrov
Fri, 05/19/2017 - 08:30 8
by Sergey Kostrov
Wed, 05/31/2017 - 08:57
Hot topic Q on memory comparison optimization (Page: 1, 2)
by Ravi K.
Fri, 04/24/2015 - 12:34 51
by andysem
Thu, 10/01/2015 - 03:29
Normal topic probable mistake in documentation---please check2
by logicman112
Sun, 09/05/2010 - 02:45 2
by logicman112
Mon, 09/13/2010 - 21:20
Normal topic Missing instruction in SSE: PSLLDQ with _bit_ shift amount?
by geofflangdale
Thu, 02/28/2008 - 15:33 4
by happyIntelCamper
Thu, 02/28/2008 - 15:33
Normal topic Size of data fetched with the instruction prefetch
by Nicolas Cadio
Wed, 01/26/2011 - 03:03 4
by Nicolas Cadio
Thu, 01/27/2011 - 05:10
Normal topic questions about such Instructions
by zhangxiuxia
Tue, 06/14/2011 - 22:53 2
by zhangxiuxia
Tue, 06/14/2011 - 22:53
Normal topic AVX512 for mobile?
by Travis D.
Wed, 09/16/2015 - 13:03 7
by McCalpin, John
Wed, 10/21/2015 - 16:06
Normal topic Detecting Nehalem CPU
by dark_shikari
Fri, 10/10/2008 - 15:24 5
by Shih Kuo (Intel)
Fri, 10/17/2008 - 18:26
Normal topic Capacity abort when using RTM provided by haswell
by zhaoguo w.
Sat, 06/15/2013 - 01:59 4
by Roman Dementiev...
Tue, 06/25/2013 - 03:48
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.