Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic Is xend treated as a full memory barrier?
by william l.
Fri, 01/13/2017 - 06:25 1
by McCalpin, John
Fri, 01/13/2017 - 11:24
Normal topic Go programs (even an empty one) hang on exit
by Peter W.
Thu, 01/05/2017 - 00:56 1
by Ady Tal (Intel)
Sun, 01/08/2017 - 01:38
Normal topic AVX512 suboptimal intrinsics compilation
by jan v.
Tue, 01/03/2017 - 09:28 7
by jan v.
Sat, 01/07/2017 - 05:28
Normal topic [XED] how to encode mov instruction
by Yuya K.
Tue, 12/27/2016 - 00:16 3
by Yuya K.
Wed, 12/28/2016 - 01:27
Normal topic AVX add slow due to vinsertf128
by CommanderLake
Sat, 12/17/2016 - 17:44 5
by CommanderLake
Tue, 12/20/2016 - 05:12
Normal topic shuffles on load ports
by Ioan H.
Tue, 12/13/2016 - 02:59 2
by Ioan H.
Mon, 12/19/2016 - 06:40
Hot topic VS2015 + SDE Debugger
by bingbing l.
Mon, 05/02/2016 - 07:19 19
by jan v.
Sat, 12/17/2016 - 05:47
Normal topic Intel(R) Parallel Studio XE 2017 emulator for linux (SDE)
by Nir H.
Tue, 12/06/2016 - 08:28 1
by Ady Tal (Intel)
Wed, 12/07/2016 - 06:37
Normal topic _mm_clmulepi64_si128 and pclmulqdq doc error
by jimdempseyatthecove
Mon, 12/05/2016 - 13:57 0
by jimdempseyatthecove
Mon, 12/05/2016 - 13:57
Normal topic AVX512 On Xeon Phi KNL using Intel Intrinsics
by Mohammad A.
Wed, 11/30/2016 - 13:15 3
by Mohammad A.
Fri, 12/02/2016 - 08:11
Normal topic AVX-512 in graph process applications
by ilya a.
Tue, 11/29/2016 - 12:19 2
by Jeremy W.
Wed, 11/30/2016 - 07:34
Normal topic How to convert two __m256d to one __m512d using intrinsics
by Zekun Y.
Sun, 10/23/2016 - 00:14 5
by areid
Wed, 11/23/2016 - 19:52
Normal topic AVX2 optimized code execution time deviation
by L K.
Wed, 11/16/2016 - 09:10 11
by L K.
Wed, 11/23/2016 - 02:56
Normal topic SDE fails to run a process
by Harald S. (Intel)
Thu, 11/03/2016 - 08:16 1
by MICHAEL G. (Intel)
Sun, 11/06/2016 - 01:41
Normal topic Retrieving/querying Intrinsic Guide
by Rashawn K. (Intel)
Thu, 10/27/2016 - 08:26 6
by jimdempseyatthecove
Sat, 11/05/2016 - 05:59
Normal topic Do Non-Temporal Loads Prefetch?
by Nicholas B.
Wed, 10/21/2015 - 02:36 9
by Jeremy W.
Sun, 10/23/2016 - 04:44
Normal topic popcount emulated for core2quads
by Axxe F.
Fri, 10/14/2016 - 01:12 1
by andysem
Fri, 10/14/2016 - 09:02
Normal topic SSE2 to AVX2 performance question
by Maria G.
Tue, 10/04/2016 - 05:51 3
by Tim P.
Thu, 10/13/2016 - 07:25
Normal topic How is the sign bit represented in memory and in the CPU?
by Marcus J.
Tue, 10/04/2016 - 09:34 2
by Marcus J.
Wed, 10/05/2016 - 21:44
Normal topic How to detect New Instruction support in the Haswell/Broadwell generation Intel® Core™ processor family
by Kumar, Amit
Mon, 10/03/2016 - 14:35 4
by andysem
Wed, 10/05/2016 - 05:08
Normal topic SDE RTM emulation - small issue
by Craig D.
Tue, 10/04/2016 - 09:49 1
by MICHAEL G. (Intel)
Wed, 10/05/2016 - 02:20
Normal topic MOV CR8 not serializing?
by Perf S.
Fri, 09/23/2016 - 15:39 0
by Perf S.
Fri, 09/23/2016 - 15:39
Normal topic Updated ISE doc, rev 25 & PCOMMIT change blog
by Mark Charney (Intel)
Wed, 09/14/2016 - 10:26 4
by Mark Charney (Intel)
Thu, 09/15/2016 - 08:58
Normal topic movd instruction not working with Masm 8.0
by slider77
Wed, 07/22/2009 - 14:04 2
by Ogilvie, Duncan
Thu, 09/08/2016 - 13:32
Normal topic SDE: ssc-marks and multiple mix output
by Othman Bouizi (...
Mon, 09/05/2016 - 03:24 0
by Othman Bouizi (...
Mon, 09/05/2016 - 03:24
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For more complete information about compiler optimizations, see our Optimization Notice.