Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic Microinstruction Format
by dargueta
Sat, 07/12/2008 - 22:41 4
by dargueta
Tue, 07/15/2008 - 19:50
Normal topic AVX VBROADCAST instructions. Why is register operand not allowed?
by Agner
Mon, 07/14/2008 - 02:52 6
by Shih Kuo (Intel)
Mon, 07/14/2008 - 02:52
Normal topic CPU temperature Pentium 4
by abdekker
Wed, 06/18/2008 - 10:07 1
by Igor Levicki
Thu, 07/10/2008 - 21:01
Normal topic SSE 4.1 instructions - DPPS/EXTRACTPS
by vsachde
Sun, 07/06/2008 - 11:50 11
by lxguy
Sun, 07/06/2008 - 11:50
Normal topic Is there any methods to see contents in MMX and XMM registers?
by kalven
Mon, 06/30/2008 - 01:43 3
by srimks
Mon, 06/30/2008 - 01:43
Normal topic Where can I find comparison between SSE3 and SSE4 instruction set??
by nasayoo
Tue, 06/24/2008 - 05:48 3
by Tim P.
Tue, 06/24/2008 - 08:21
Normal topic Where can I find documents about SSE3 and SSE4 for early study?
by kalven
Thu, 06/19/2008 - 19:01 5
by srimks
Thu, 06/19/2008 - 19:01
Normal topic Anyone thinking of setting low-width integars with high-width integars?
by kalven
Mon, 06/16/2008 - 01:56 2
by kalven
Thu, 06/19/2008 - 18:52
Normal topic SSE Optimization
by mpdelbuono
Thu, 06/19/2008 - 06:43 2
by Shih Kuo (Intel)
Thu, 06/19/2008 - 10:50
Hot topic sse execution units in core duo
by s.gautam
Wed, 06/18/2008 - 04:23 23
by maa1
Wed, 06/18/2008 - 04:23
Normal topic Int64 <-> double conversion with SSE?
by pvercello
Sat, 06/07/2008 - 02:33 6
by wmula
Fri, 06/13/2008 - 17:50
Normal topic performance issues with SSE2
by s.gautam
Tue, 06/10/2008 - 11:41 3
by Tim P.
Tue, 06/10/2008 - 11:41
Normal topic CPU recommendation?
by audiobahn1000
Fri, 05/30/2008 - 03:16 1
by Igor Levicki
Fri, 05/30/2008 - 03:16
Normal topic SSE3 critique
by Deleted User
Fri, 08/19/2005 - 08:35 3
by Igor Levicki
Tue, 05/27/2008 - 09:59
Normal topic crc32 emulation support
by tinman8088
Sun, 05/25/2008 - 21:28 3
by Igor Levicki
Sun, 05/25/2008 - 21:28
Normal topic Question about the PUSH instruction
by millersd
Wed, 04/30/2008 - 15:55 2
by millersd
Tue, 05/13/2008 - 07:56
Normal topic looking for information sources on code optimization using the Intel CPU and the MMX/SSE family instruction set
by amoshkov
Fri, 05/09/2008 - 12:21 4
by srimks
Fri, 05/09/2008 - 12:21
Normal topic AVX simulator?
by syoyo
Sat, 04/26/2008 - 03:11 4
by syoyo
Sat, 04/26/2008 - 03:11
Normal topic Welcome to the Intel(R) AVX Forum!
by aaron-tersteeg ...
Wed, 04/02/2008 - 12:36 8
by Thai Le (Intel)
Mon, 04/21/2008 - 22:02
Normal topic Intel Intrinsic Guide on Linux. Why not?
by jose angel m.
Mon, 04/21/2008 - 12:16 1
by srimks
Mon, 04/21/2008 - 12:16
Normal topic gcc and avx
by (name withheld)
Sun, 04/20/2008 - 16:51 2
by srimks
Sun, 04/20/2008 - 16:51
Normal topic Questions about AVX
by Igor Levicki
Fri, 04/04/2008 - 11:11 8
by Igor Levicki
Fri, 04/04/2008 - 11:11
Normal topic Excuting time of the instruction "rdtsc" on X86
by dhbellwyc
Tue, 03/11/2008 - 06:12 4
by dhbellwyc
Tue, 03/11/2008 - 06:12
Normal topic Missing instruction in SSE: PSLLDQ with _bit_ shift amount?
by geofflangdale
Thu, 02/28/2008 - 15:33 4
by happyIntelCamper
Thu, 02/28/2008 - 15:33
Normal topic RDTSC variability in Core 2 Quad
by agame
Fri, 02/08/2008 - 19:31 1
by Tim P.
Sat, 02/09/2008 - 06:21
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.