Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic startersort descending Post date Replies Last Post
Normal topic Weeks of optimizations and still can't beat the intel compiler
by mr_nuke
Fri, 02/19/2010 - 08:34 9
by tthsqe
Fri, 02/19/2010 - 08:38
Normal topic Weird BTS Performance
by cwillems
Fri, 06/10/2011 - 07:25 5
by Hussam Mousa (Intel)
Fri, 06/10/2011 - 07:25
Normal topic Welcome to the Intel(R) AVX Forum!
by aaron-tersteeg ...
Wed, 04/02/2008 - 12:36 8
by Thai Le (Intel)
Mon, 04/21/2008 - 22:02
Normal topic What are the alignment restrictions on the new Haswell AVX VGATHER instructions ?
by Tim Day
Fri, 07/01/2011 - 02:59 2
by bronxzv
Fri, 07/01/2011 - 15:32
Normal topic What is (name withheld)?
by andysem
Wed, 01/20/2016 - 00:48 2
by iliyapolak
Thu, 01/21/2016 - 01:55
Normal topic What is behavior of LD + OP instruction with register source and EVEX.b = 1?
by Michael R.
Thu, 09/10/2015 - 00:44 0
by Michael R.
Thu, 09/10/2015 - 00:44
Normal topic What is syntax for broadcast decorator?
by Michael R.
Sun, 07/26/2015 - 17:51 3
by Alexander F. (Intel)
Thu, 07/30/2015 - 10:49
Normal topic What is the best way to sum up values in __m256 ?
by zlw
Mon, 09/26/2011 - 16:21 5
by sirrida
Tue, 09/27/2011 - 12:38
Normal topic What is the latency and throughput of the vbroadcastsd instruction?
by jeremyweek
Mon, 06/06/2011 - 10:43 1
by c0d1f1ed
Mon, 06/06/2011 - 10:43
Normal topic What is the limit of ICC ?
by zhangxiuxia
Fri, 02/24/2012 - 17:31 1
by Steve Lionel (Intel)
Sun, 02/26/2012 - 11:31
Normal topic What is the status of VZEROUPPER use?
by Agner
Fri, 11/25/2016 - 12:22 8
by Agner
Wed, 12/28/2016 - 02:30
Normal topic What is _MM_SHUFFLE macro meaning in the context of AVX
by Hien P.
Tue, 08/26/2014 - 21:44 2
by Hien P.
Wed, 08/27/2014 - 17:28
Normal topic what micro-operations (uops) instruction decoded?
by zhangxiuxia
Wed, 05/18/2011 - 07:33 3
by iliyapolak
Mon, 09/23/2013 - 07:24
Normal topic What's the best way to sum up values in __m128 ?
by zlw
Thu, 02/10/2011 - 15:23 1
by Matthias Kretz
Thu, 02/10/2011 - 15:23
Normal topic When is AVX 512 on a chip, not just an emulator?
by Thomas H.
Tue, 07/01/2014 - 05:06 4
by bronxzv
Fri, 08/08/2014 - 04:37
Normal topic Where can I find comparison between SSE3 and SSE4 instruction set??
by nasayoo
Tue, 06/24/2008 - 05:48 3
by Tim P.
Tue, 06/24/2008 - 08:21
Normal topic Where can I find documents about SSE3 and SSE4 for early study?
by kalven
Thu, 06/19/2008 - 19:01 5
by srimks
Thu, 06/19/2008 - 19:01
Normal topic where can i find the whole instruction set of sandybridge?
by Lin W.
Mon, 12/10/2012 - 00:41 3
by iliyapolak
Sat, 01/05/2013 - 22:53
Normal topic where can I get the reference of pseudo-code?
by Raymond S.
Wed, 02/24/2016 - 18:27 4
by iliyapolak
Fri, 03/11/2016 - 01:57
Normal topic Where to Find Intel MMX SIMD Examples
by iekpo
Thu, 02/11/2010 - 13:37 4
by iekpo
Fri, 02/19/2010 - 11:46
Normal topic Which AVX instructions are 256-bit enabled on SNB-EP?
by (name withheld)
Tue, 08/09/2011 - 16:52 8
by Tim P.
Thu, 08/11/2011 - 16:03
Normal topic Which instructions behavior differently between VMX mode and Virtual-8086 Mode
by hurricanezhb
Sat, 08/22/2009 - 04:33 0
by hurricanezhb
Sat, 08/22/2009 - 04:33
Normal topic Why "subq" as allocate by ICC-v10.0 but not as prologue, but ICC-v11.0 uses "pushq" as prologue?
by srimks
Wed, 01/21/2009 - 01:10 3
by Sergey Maslov (...
Mon, 11/02/2009 - 22:18
Normal topic Why AVX do not support real/V86 mode
by yuhong2
Thu, 04/23/2009 - 23:44 1
by Thai Le (Intel)
Thu, 04/23/2009 - 23:44
Normal topic why does _mm_mulhrs_epi16() always do biased rounding to positive infinity?
by unclejoe
Fri, 01/30/2015 - 19:25 9
by iliyapolak
Fri, 02/06/2015 - 12:07
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For more complete information about compiler optimizations, see our Optimization Notice.