Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic startersort descending Post date Replies Last Post
Normal topic SSE2 - Class crash with SSE related members
by obscurity
Thu, 06/05/2008 - 04:54 13
by Igor Levicki
Sun, 07/27/2008 - 19:54
Normal topic SSE2 help needed
by rheikon
Fri, 09/30/2005 - 21:36 13
by Community Admin
Mon, 10/03/2005 - 20:59
Normal topic sse2 intrinsic equivalent
by Smart Lubobya
Mon, 08/16/2010 - 09:06 7
by neni
Fri, 09/03/2010 - 15:52
Normal topic SSE2 to AVX2 performance question
by Maria G.
Tue, 10/04/2016 - 05:51 3
by Tim P.
Thu, 10/13/2016 - 07:25
Normal topic SSE2 vectorized code seems to run slower than non-vectorized code
by acctpurge a.
Thu, 07/11/2013 - 08:05 12
by iliyapolak
Sun, 07/28/2013 - 02:40
Normal topic SSE3 and onwards support...
by srimks
Tue, 08/25/2009 - 05:20 1
by Tim P.
Tue, 08/25/2009 - 05:20
Normal topic SSE3 critique
by Deleted User
Fri, 08/19/2005 - 08:35 3
by Igor Levicki
Tue, 05/27/2008 - 09:59
Normal topic SSE4
by hjazz
Mon, 01/25/2010 - 23:28 2
by hjazz
Tue, 01/26/2010 - 17:30
Normal topic SSE4 is there a BigInt LIbrary?
by gbrun
Wed, 10/12/2011 - 21:03 3
by styc
Fri, 10/14/2011 - 22:35
Normal topic SSE4 Intrensics on Visual Studio 2008
by Uday Krishna G.
Wed, 07/30/2014 - 23:50 6
by Thomas Willhalm...
Fri, 08/01/2014 - 04:53
Hot topic SSE4 Register-Handling
by adrian s.
Wed, 07/10/2013 - 07:58 21
by Sergey Kostrov
Thu, 07/18/2013 - 18:38
Normal topic SSE4.2 cpuid support found in Pin/SDE on Intel but not on AMD...
by perfwise
Thu, 08/26/2010 - 15:00 3
by Mark Charney (Intel)
Thu, 08/26/2010 - 15:01
Normal topic sse4.2 instructions
by westmere
Fri, 05/01/2009 - 16:03 7
by Shih Kuo (Intel)
Mon, 11/02/2009 - 09:54
Normal topic SSSE3 intrinsics compilation error on x64 VC++ 2005 platform
by biplabraut
Tue, 01/20/2009 - 03:01 1
by gabest
Tue, 01/20/2009 - 03:01
Normal topic ssse3+ shuffle instruction
by mustache_marc
Thu, 02/24/2011 - 02:38 2
by denbianh
Thu, 02/24/2011 - 02:38
Normal topic stack around variable x, sse2 intrinsic codes
by Smart Lubobya
Sun, 08/01/2010 - 05:02 1
by neni
Sun, 08/01/2010 - 05:02
Normal topic State of AVX 512 on Skylake-X
by jan v.
Sat, 07/08/2017 - 02:17 8
by jan v.
Thu, 09/07/2017 - 09:02
Hot topic Storing data is bottleneck?
by Arthur U.
Wed, 01/09/2013 - 02:31 17
by Sergey Kostrov
Mon, 04/15/2013 - 16:56
Normal topic Storing data is bottleneck?
by Arthur U.
Wed, 01/09/2013 - 02:31 4
by McCalpin, John
Tue, 03/04/2014 - 12:18
Normal topic Strange IPC behavior
by Patrick P.
Sun, 10/19/2014 - 13:11 5
by Patrick P.
Tue, 10/21/2014 - 04:44
Normal topic strlen with SSE4.2 instructions
by wmula
Sat, 06/07/2008 - 15:10 2
by Shih Kuo (Intel)
Mon, 07/21/2008 - 22:47
Normal topic Studying Intel TSX Performance: strange results
by Alexander K.
Mon, 11/11/2013 - 14:13 9
by jimdempseyatthecove
Mon, 12/30/2013 - 05:08
Normal topic Suggestion about memory-access-signaling mechanism
by Luchezar B.
Sat, 11/29/2014 - 03:48 3
by Luchezar B.
Thu, 12/11/2014 - 10:58
Normal topic Support for saturation and addition instruction in AVX-512
by Udupi, Nagacharan
Mon, 03/19/2018 - 12:39 1
by Christopher H.
Sun, 05/06/2018 - 01:01
Normal topic Supported processors for PTWRITE instruction?
by Muhammad Usman N.
Wed, 11/30/2016 - 11:37 2
by BEEMAN S. (Intel)
Fri, 02/17/2017 - 12:50
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.