Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Post
Hot topic How to extract DWORD from upper half of 256-bit register? (Page: 1, 2)
by Igor Levicki
Tue, 07/02/2013 - 04:51 63
by iliyapolak
Tue, 12/17/2013 - 13:04
Normal topic Inconsistency between sections 4.6.1 and 4.6.2 Vol 3A (Paging)
by Mohan, Vish
Tue, 02/16/2016 - 14:20 1
by David Koufaty (...
Mon, 02/22/2016 - 14:19
Normal topic Possible issues with VPMOVSXWD (VEX.256)
by Eli Hernandez (...
Wed, 08/25/2010 - 13:17 2
by Brijender Bhart...
Wed, 08/25/2010 - 14:39
Normal topic Getting aligned accesses with AVX/SSE
by Fabio L.
Mon, 12/17/2012 - 16:28 7
by Tim P.
Wed, 12/19/2012 - 08:59
Normal topic SDE produces unstable behavior
by andysem
Mon, 03/31/2014 - 03:26 2
by andysem
Tue, 04/01/2014 - 01:45
Normal topic What is the status of VZEROUPPER use?
by Agner
Fri, 11/25/2016 - 12:22 11
by Lee K. (Intel)
Thu, 06/29/2017 - 18:40
Normal topic MP (multi-processor) system - LAPIC query
by mguptamel
Mon, 01/10/2011 - 19:04 2
by Chris Hooper
Fri, 05/20/2011 - 23:39
Normal topic PCIe Root Complex and the PCH
by Robert S.
Fri, 12/19/2014 - 16:36 3
by Robert S.
Tue, 12/23/2014 - 17:40
Normal topic Calculate Miss rate of L2 cache given global and L1 miss rates
by Papote J.
Sun, 05/07/2017 - 12:54 0
by Papote J.
Sun, 05/07/2017 - 12:54
Normal topic bit interleave instruction
by torusle
Sat, 05/17/2008 - 16:33 9
by sirrida
Wed, 07/04/2012 - 04:37
Normal topic What is the latency and throughput of the vbroadcastsd instruction?
by jeremyweek
Mon, 06/06/2011 - 10:43 1
by c0d1f1ed
Mon, 06/06/2011 - 10:43
Normal topic New version of Intel(R) SDE posted
by Mark Charney (Intel)
Mon, 01/12/2009 - 06:14 1
by aaron-tersteeg ...
Mon, 01/12/2009 - 06:15
Normal topic does pentium E5300 have 2 physical cores ?
by ilbeydinler
Thu, 02/25/2010 - 13:13 2
by ilbeydinler
Thu, 02/25/2010 - 14:00
Normal topic AVX2 support in IACA
by bronxzv
Sat, 01/14/2012 - 04:38 7
by Patrick Konsor ...
Thu, 02/02/2012 - 09:40
Normal topic float min_reduce(__m128 x)
by Matthias Kretz
Fri, 06/05/2009 - 03:30 3
by Matthias Kretz
Fri, 06/05/2009 - 03:30
Normal topic intel phi bandwith
by Guangming T.
Wed, 04/10/2013 - 20:56 2
by iliyapolak
Wed, 04/10/2013 - 22:55
Hot topic Massive speedup of integer SSE2 code using AVX1(!)
by Nikos D.
Sun, 09/06/2015 - 22:32 28
by iliyapolak
Wed, 12/16/2015 - 12:58
Normal topic MMX ARRAY ADDITION
by Smart Lubobya
Sun, 07/11/2010 - 03:51 1
by lordmonsoon
Sun, 07/11/2010 - 03:51
Normal topic MASM files + Intel compiler/assembler in Linux
by chekib
Thu, 07/12/2012 - 11:26 1
by Sergey Kostrov
Tue, 07/17/2012 - 19:59
Normal topic How to multiply __m128 by a scaler?
by lascondes
Wed, 09/30/2009 - 11:30 11
by lascondes
Wed, 09/30/2009 - 11:30
Normal topic Adding consecutive large numbers
by Angelos P.
Tue, 04/30/2013 - 06:33 5
by Sergey Kostrov
Thu, 05/02/2013 - 07:31
Normal topic IA-32e 64-bit and compatibility mode
by Ravi K.
Tue, 09/15/2015 - 05:12 3
by Ravi K.
Wed, 09/30/2015 - 12:26
Normal topic MOVD: Zero-extension of general purpose register as destination
by Adam Warner
Mon, 07/12/2010 - 23:41 2
by Adam Warner
Mon, 07/12/2010 - 23:41
Normal topic Problems encountred during vectorization of code using SSE intrinsics
by priyanka06
Mon, 07/23/2012 - 08:14 2
by jimdempseyatthecove
Sun, 09/09/2012 - 17:15
Normal topic Parallel instructions for detecting MSB in array of bytes
by craptacus
Thu, 10/15/2009 - 12:56 6
by bronxzv
Fri, 10/16/2009 - 01:58
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For more complete information about compiler optimizations, see our Optimization Notice.