Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic Question about write SIMD code mannually
by Raymond S.
Fri, 04/22/2016 - 00:35 1
by McCalpin, John
Fri, 04/22/2016 - 10:57
Normal topic Intel 64 documentation bug
by Chris S.
Tue, 03/10/2015 - 17:27 1
by Mark Charney (Intel)
Tue, 03/10/2015 - 19:19
Normal topic RDRAND instruction supported but DRNG not supported
by SathyaShankar K.
Mon, 08/08/2016 - 23:57 1
by Mark Charney (Intel)
Tue, 08/23/2016 - 08:09
Normal topic Why only CS, IP and EFLAGS are saved while interrupt??
by cgopi24
Fri, 09/25/2009 - 09:29 1
by Shih Kuo (Intel)
Fri, 10/16/2009 - 01:34
Normal topic Why AVX code slower then native C++ code ?
by Jorn V.
Sat, 09/30/2017 - 03:49 1
by Cownie, James H...
Mon, 10/02/2017 - 01:56
Normal topic Intel manual has some mistakes
by logicman112
Sat, 06/26/2010 - 21:01 1
by logicman112
Sat, 06/26/2010 - 21:01
Normal topic CPU temperature Pentium 4
by abdekker
Wed, 06/18/2008 - 10:07 1
by Igor Levicki
Thu, 07/10/2008 - 21:01
Normal topic MMX ARRAY ADDITION
by Smart Lubobya
Sun, 07/11/2010 - 03:51 1
by lordmonsoon
Sun, 07/11/2010 - 03:51
Normal topic MASM files + Intel compiler/assembler in Linux
by chekib
Thu, 07/12/2012 - 11:26 1
by Sergey Kostrov
Tue, 07/17/2012 - 19:59
Normal topic Inconsistency between sections 4.6.1 and 4.6.2 Vol 3A (Paging)
by Mohan, Vish
Tue, 02/16/2016 - 14:20 1
by David Koufaty (...
Mon, 02/22/2016 - 14:19
Normal topic Selector to gate ?
by carsten2
Mon, 07/20/2009 - 20:17 1
by Shih Kuo (Intel)
Thu, 08/06/2009 - 15:40
Normal topic Timing of LPT-port
by ugtehservis
Wed, 09/03/2008 - 23:36 1
by Igor Levicki
Tue, 09/30/2008 - 17:35
Normal topic Why AVX do not support real/V86 mode
by yuhong2
Thu, 04/23/2009 - 23:44 1
by Thai Le (Intel)
Thu, 04/23/2009 - 23:44
Normal topic 64-ia-32 instruction reference manual --- FXAM description incorrect?
by Andres V.
Wed, 05/04/2016 - 03:44 1
by Mark Charney (Intel)
Wed, 05/04/2016 - 06:24
Normal topic AVX with faster memory
by magicfoot
Tue, 10/25/2011 - 10:41 1
by Max Locktyukhin...
Tue, 10/25/2011 - 13:00
Normal topic Any docs or manuals about MPK(memory protection keys)
by Du D.
Fri, 07/28/2017 - 20:01 1
by Mark Charney (Intel)
Mon, 07/31/2017 - 06:51
Normal topic New version of Intel(R) SDE posted
by Mark Charney (Intel)
Mon, 01/12/2009 - 06:14 1
by aaron-tersteeg ...
Mon, 01/12/2009 - 06:15
Normal topic Error code of einit
by gu j.
Mon, 01/04/2016 - 05:33 1
by Simon Johnson (...
Mon, 01/04/2016 - 07:51
Normal topic What is the latency and throughput of the vbroadcastsd instruction?
by jeremyweek
Mon, 06/06/2011 - 10:43 1
by c0d1f1ed
Mon, 06/06/2011 - 10:43
Normal topic small typo in Intel® 64 and IA-32 Architectures Software Developer’s Manual
by Bea T.
Tue, 06/30/2015 - 02:31 1
by Mark Charney (Intel)
Tue, 06/30/2015 - 05:22
Normal topic Transpose for 4x4 Matrix(double)
by Shaquille W.
Sat, 10/21/2017 - 23:03 1
by McCalpin, John
Mon, 10/23/2017 - 14:12
Normal topic Difference between L2 cache misses and Bus_Trans_Mem
by gokussj9
Mon, 09/27/2010 - 15:13 1
by neni
Mon, 09/27/2010 - 15:13
Normal topic Obtain time stamp disable (TSD) flag in user-mode
by freeze2046
Tue, 03/29/2011 - 05:54 1
by Chris Hooper
Tue, 03/29/2011 - 05:54
Normal topic Bug in SDE emulation of AVX-512 _mm512_permutevar_ps() ?
by Romain D.
Wed, 04/30/2014 - 01:08 1
by Romain D.
Wed, 04/30/2014 - 01:27
Normal topic Interpreting Intel SDE avx/sse transition tracker
by Bram S.
Thu, 01/08/2015 - 12:25 1
by Mark Charney (Intel)
Thu, 01/08/2015 - 12:39
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For more complete information about compiler optimizations, see our Optimization Notice.