Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

Topic / Topic starter Post datesort descending Replies Last Post
Normal topic encoding disp32 in Amd64
by anujgarg2004gma...
Tue, 06/23/2009 - 04:57 2
by anujgarg2004gma...
Tue, 06/23/2009 - 10:09
Normal topic Do the Intel 11.1 compilers support AVX?
by twilkens
Wed, 06/24/2009 - 17:08 5
by twilkens
Wed, 06/24/2009 - 17:08
Normal topic x64/ia64 Assemly Instructions in Code Porting
by gangti
Wed, 07/01/2009 - 20:18 3
by jimdempseyatthecove
Wed, 07/01/2009 - 20:18
Normal topic Can assembly function written with AVX instructions be built for running on corei7?
by satheesan
Fri, 07/03/2009 - 00:25 2
by satheesan
Sun, 07/05/2009 - 20:29
Normal topic CPU enhancement wish list
by youjaes
Sun, 07/05/2009 - 01:37 6
by jimdempseyatthecove
Sun, 07/05/2009 - 01:37
Normal topic Help an Assembler Noob, it's good karma
by tyrch
Tue, 07/07/2009 - 16:06 6
by Agner
Tue, 07/07/2009 - 16:06
Normal topic quad core q9550 question
by threetwo
Wed, 07/08/2009 - 09:47 0
by threetwo
Wed, 07/08/2009 - 09:47
Normal topic __libm_sse2_sincos
by srimks
Mon, 07/13/2009 - 09:32 9
by srimks
Mon, 07/13/2009 - 20:47
Normal topic Behaviour of instructions on 32bit operands in 64 bit mode
by anujgarg2004gma...
Mon, 07/20/2009 - 02:33 4
by carsten2
Mon, 07/20/2009 - 02:33
Normal topic Selector to gate ?
by carsten2
Mon, 07/20/2009 - 20:17 1
by Shih Kuo (Intel)
Thu, 08/06/2009 - 15:40
Normal topic Intel SIMD - Processor Roadmap
by leec
Tue, 07/21/2009 - 23:10 3
by leec
Tue, 07/21/2009 - 23:10
Normal topic movd instruction not working with Masm 8.0
by slider77
Wed, 07/22/2009 - 14:04 1
by mazegen
Wed, 07/22/2009 - 14:04
Normal topic RBX: Segmentation Error.
by srimks
Tue, 07/28/2009 - 09:04 3
by Shih Kuo (Intel)
Tue, 07/28/2009 - 09:09
Normal topic Generating Prefetch Instructions in AVX code...
by twilkens
Thu, 07/30/2009 - 10:49 5
by Martyn Corden (...
Tue, 08/04/2009 - 11:40
Normal topic CPU Instruction counter register
by nuclear_scientist
Fri, 07/31/2009 - 09:37 1
by Tim Prince
Fri, 07/31/2009 - 09:37
Normal topic Deprecate x87 FPU?
by jeff_keasler
Mon, 08/03/2009 - 22:04 1
by Tim Prince
Mon, 08/03/2009 - 22:30
Normal topic Intel C++ : _mm256_set1_ps suboptimal ?
by bronxzv
Sun, 08/09/2009 - 15:45 0
by bronxzv
Sun, 08/09/2009 - 15:45
Normal topic Prologue & Epilogue Help
by srimks
Mon, 08/10/2009 - 01:38 0
by srimks
Mon, 08/10/2009 - 01:38
Normal topic Inline asm
by srimks
Mon, 08/10/2009 - 05:00 3
by srimks
Mon, 08/10/2009 - 05:00
Normal topic optimal ordering of instructions
by tthsqe
Mon, 08/10/2009 - 20:16 0
by tthsqe
Mon, 08/10/2009 - 20:16
Normal topic Opcode semantics
by matt.j
Thu, 08/13/2009 - 18:24 3
by c0d1f1ed
Mon, 11/02/2009 - 00:38
Normal topic .S help
by srimks
Mon, 08/17/2009 - 14:47 0
by srimks
Mon, 08/17/2009 - 14:47
Normal topic Which instructions behavior differently between VMX mode and Virtual-8086 Mode
by hurricanezhb
Sat, 08/22/2009 - 04:33 0
by hurricanezhb
Sat, 08/22/2009 - 04:33
Normal topic SSE3 and onwards support...
by srimks
Tue, 08/25/2009 - 05:20 1
by Tim Prince
Tue, 08/25/2009 - 05:20
Normal topic determining L1 and L2 cache state
by maamold
Tue, 08/25/2009 - 10:00 0
by maamold
Tue, 08/25/2009 - 10:00
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Hot topic with new posts
Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.