Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

Topic / Topic starter Post date Repliessort descending Last Post
Normal topic Cache memory
by prakasht
Sat, 09/25/2010 - 19:21 1
by Tim Prince
Mon, 09/27/2010 - 05:46
Normal topic PADDW __m128i _mm_add_epi16 ( __m128i a, __m128i b) doubt
by inteleverywhere
Fri, 07/30/2010 - 01:04 1
by Brijender Bhart...
Fri, 07/30/2010 - 10:28
Normal topic What is the limit of ICC ?
by zhangxiuxia
Fri, 02/24/2012 - 17:31 1
by Steve Lionel (Intel)
Sun, 02/26/2012 - 11:31
Normal topic Compute eflags
by hunter123
Tue, 06/17/2008 - 14:00 1
by Igor Levicki
Sun, 07/27/2008 - 20:36
Normal topic elemental functions for Fortan?
by eimunic
Mon, 11/07/2011 - 07:08 1
by Steve Lionel (Intel)
Fri, 12/02/2011 - 14:07
Normal topic Ooops - wrong instruction description in volume 2 of the SDM
by John D. McCalpin
Thu, 07/02/2015 - 11:39 1
by Mark Charney (Intel)
Thu, 07/02/2015 - 12:20
Normal topic Update Bios lennovo t400
by hoapq
Thu, 02/25/2010 - 23:29 1
by Thomas Willhalm...
Thu, 02/25/2010 - 23:29
Normal topic icpc avx optimization
by forum.san@gmail.com
Wed, 01/02/2013 - 10:06 1
by Tim Prince
Wed, 01/02/2013 - 13:07
Normal topic Intel AVX on Microsoft Windows Vista
by inteleverywhere
Mon, 07/04/2011 - 22:52 1
by Tim Prince
Mon, 07/04/2011 - 22:52
Normal topic Intel 64 documentation bug
by Chris S.
Tue, 03/10/2015 - 17:27 1
by Mark Charney (Intel)
Tue, 03/10/2015 - 19:19
Normal topic LZCNT on Core i7
by craigj0
Mon, 10/12/2009 - 04:29 1
by Mark Charney (Intel)
Mon, 10/12/2009 - 04:29
Normal topic Performance of SHA-3 hash functions on Intel processors (Core 2 platform vs Itanium)
by gligoroski
Wed, 04/21/2010 - 07:18 1
by gligoroski
Wed, 04/21/2010 - 07:20
Normal topic Documentation suggestion
by jimdempseyatthecove
Fri, 02/06/2009 - 07:15 1
by Shih Kuo (Intel)
Fri, 02/06/2009 - 07:15
Normal topic Replacement of packusdw
by c0d1f1ed
Thu, 06/04/2009 - 03:50 1
by neni
Thu, 06/04/2009 - 03:50
Normal topic Use AVX; fallback to SSE4.2
by Levi Morrison
Wed, 11/07/2012 - 11:05 1
by Tim Prince
Wed, 11/07/2012 - 18:09
Normal topic vertical sync
by dido88
Wed, 06/01/2011 - 11:39 1
by Thomas Willhalm...
Wed, 06/01/2011 - 11:39
Normal topic Interpreting Intel SDE avx/sse transition tracker
by Bram S.
Thu, 01/08/2015 - 12:25 1
by Mark Charney (Intel)
Thu, 01/08/2015 - 12:39
Normal topic adding a constant to array addition in sse2
by Smart Lubobya
Sun, 07/25/2010 - 07:19 1
by Brijender Bhart...
Tue, 07/27/2010 - 11:13
Normal topic FMA manipulation of register’s content for XMM, YMM and ZMM register sets
by Mile M.
Tue, 01/21/2014 - 19:23 1
by Mile M.
Tue, 01/21/2014 - 19:45
Normal topic __int64 data types
by Smart Lubobya
Sat, 09/18/2010 - 22:19 1
by Tim Prince
Sat, 09/18/2010 - 22:20
Normal topic _mm_lddqu_si128 and _mm_loadu_si128
by ivantsou
Tue, 09/28/2010 - 10:51 1
by neni
Tue, 09/28/2010 - 13:59
Normal topic Is there an error in Operation pseudo-code for FSIN instruction?
by Sergey Kostrov
Mon, 07/23/2012 - 16:20 1
by iliyapolak
Mon, 07/23/2012 - 17:07
Normal topic code vectorisation
by Smart Lubobya
Sun, 08/01/2010 - 10:13 1
by Brijender Bhart...
Thu, 08/19/2010 - 17:39
Normal topic Why only CS, IP and EFLAGS are saved while interrupt??
by cgopi24
Fri, 09/25/2009 - 09:29 1
by Shih Kuo (Intel)
Fri, 10/16/2009 - 01:34
Normal topic Intel documentation seems to have wrong or ambiguous information!
by logicman112
Sun, 06/13/2010 - 21:24 1
by mecej4
Sun, 06/13/2010 - 21:24
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For more complete information about compiler optimizations, see our Optimization Notice.