Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Repliessort ascending Last Post
Normal topic Studying Intel TSX Performance: strange results
by Alexander K.
Mon, 11/11/2013 - 14:13 9
by jimdempseyatthecove
Mon, 12/30/2013 - 05:08
Normal topic REAL(16) - long double
by jimdempseyatthecove
Fri, 02/06/2009 - 07:41 9
by jimdempseyatthecove
Wed, 02/11/2009 - 12:14
Normal topic why does _mm_mulhrs_epi16() always do biased rounding to positive infinity?
by unclejoe
Fri, 01/30/2015 - 19:25 9
by iliyapolak
Fri, 02/06/2015 - 12:07
Normal topic bit interleave instruction
by torusle
Sat, 05/17/2008 - 16:33 9
by sirrida
Wed, 07/04/2012 - 04:37
Normal topic ippGetCpuFeatures for AVX2 support
by bronxzv
Sun, 03/09/2014 - 09:47 9
by bronxzv
Wed, 03/12/2014 - 16:19
Normal topic Weeks of optimizations and still can't beat the intel compiler
by mr_nuke
Fri, 02/19/2010 - 08:34 9
by tthsqe
Fri, 02/19/2010 - 08:38
Normal topic Understanding tsx abort results from the SDE
by Keith C.
Tue, 01/12/2016 - 10:55 9
by Roman Dementiev...
Fri, 05/06/2016 - 08:29
Normal topic Check if a floating point is actually an Integer
by anujgarg2004gma...
Wed, 01/07/2009 - 09:41 9
by Igor Levicki
Wed, 01/07/2009 - 09:41
Normal topic __libm_sse2_sincos
by srimks
Mon, 07/13/2009 - 09:32 9
by srimks
Mon, 07/13/2009 - 20:47
Normal topic Efficient ways to count setted bits in bytes/words?
by q w.
Tue, 01/22/2013 - 18:48 9
by Sergey Kostrov
Fri, 01/25/2013 - 07:15
Normal topic Intel C++ Compiler (Linux x86_64) - "GNU-style Inline Assembly" Resources.
by srimks
Mon, 05/25/2009 - 11:01 9
by srimks
Mon, 05/25/2009 - 16:57
Normal topic how aligned class data member,
by Timocafe
Wed, 10/27/2010 - 03:16 9
by Gaiger Chen
Wed, 10/27/2010 - 03:44
Normal topic Question about latency
by Alexander L.
Sun, 01/29/2017 - 07:09 9
by Todd West
Sun, 02/12/2017 - 15:14
Normal topic Do Non-Temporal Loads Prefetch?
by Nicholas B.
Wed, 10/21/2015 - 02:36 9
by Jeremy W.
Sun, 10/23/2016 - 04:44
Normal topic avx instruction choice
by zhangxiuxia
Mon, 02/20/2012 - 04:55 9
by Max Locktyukhin...
Wed, 02/22/2012 - 18:41
Normal topic New Xeons on Intel Ark
by emmanuel.attia
Tue, 09/09/2014 - 02:28 9
by Tim P.
Fri, 09/12/2014 - 07:39
Normal topic Need help: Why my avx code is slower than SSE code?
by Chen S.
Sun, 06/08/2014 - 04:38 8
by emmanuel.attia
Mon, 06/16/2014 - 09:45
Normal topic Cache Optimization
by xift
Thu, 05/06/2010 - 03:48 8
by Thomas Willhalm...
Thu, 05/06/2010 - 03:48
Normal topic Poor Code Gen of FMA3 instructions in SPEC FP 06 using Intel 14.0.0 compiler suite
by perfwise
Wed, 10/02/2013 - 07:10 8
by perfwise
Fri, 10/04/2013 - 12:04
Normal topic knowing whether AVX or AVX2 is used.
by Po-yen C. (Intel)
Wed, 01/13/2016 - 15:56 8
by Po-yen C. (Intel)
Thu, 01/14/2016 - 14:43
Normal topic Core 2 MSR register documentation
by elmo234
Tue, 06/17/2008 - 10:24 8
by yuhong2
Mon, 02/01/2010 - 20:48
Normal topic Array of _m128d values as function argument
by n.anastop
Tue, 03/19/2013 - 06:43 8
by iliyapolak
Fri, 03/22/2013 - 05:42
Normal topic PUSH and POP of XMM/YMM registers
by srinivasu
Wed, 06/18/2014 - 04:57 8
by iliyapolak
Thu, 06/19/2014 - 05:42
Normal topic Converting SSE packed integer handling to AVX
by Grace Oliver (Intel)
Tue, 08/09/2011 - 15:26 8
by Grace Oliver (Intel)
Fri, 08/19/2011 - 12:02
Normal topic Intel® Xeon Phi™ x200 series (KNL) Ring 3 Monitor/MWait
by Cownie, James H
Thu, 10/13/2016 - 02:04 8
by Cownie, James H
Mon, 02/06/2017 - 01:41
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For more complete information about compiler optimizations, see our Optimization Notice.